Dave,
Thank is really a fantastic resource you linked, I wish I knew it existed last week!
I am learning more every day.
I have used this guide to take a look at the pinmux .cfg file and find the line that I think I am concerned with:
I think Header pin 18 corresponds to signal soc_gpio12 according to pinmux spreadsheet.
So, there is a line in my custom pinmux .cfg here:
pinmux.0x02434090 = 0x00000405; # soc_gpio12_ph0: gp, pull-down, tristate-disable, input-disable, lpdr-disable
In the original one, it reads:
pinmux.0x02434090 = 0x00000054; # soc_gpio12_ph0: rsvd0, pull-down, tristate-enable, input-enable, lpdr-disable
So it appears I am changing something.
I am flashing with:
sudo ./flash.sh -k MB1_BCT jetson-xavier mmcblk0p1
and changing the file:
Linux_for_Tegra/bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a00-p2822-0000-a00.cfg
`
Note I am not changing any padvoltage related files, as it does not seem that I have to?
Further, once I flash MB1_BCT and boot, I used devmem2 to check the register:
dev@tegra-ubuntu:~/jetson-gpio/samples$ sudo devmem2 0x02434090 /dev/mem opened. Memory mapped at address 0xffffa139a000. Value at address 0x2434090 (0xffffa139a090): 0x401
Which is similar but not the same as the 0x00000405 I was expecting. I guess there could a prod / other .cfg file overwriting this change?
Also do these pinmux settings look correct for setting PWM5? I would have expected some reference to the GP_PWM5 or something.
Further, if I flash the original .cfg file that comes with the BSP, The value is the same.
dev@tegra-ubuntu:~$ sudo devmem2 0x02434090 /dev/mem opened. Memory mapped at address 0xffff80023000. Value at address 0x2434090 (0xffff80023090): 0x401
I think I am getting close to a solution to my problem, so a couple more pointers would be greatly appreciated. Configuring pinmux is a first for me as you can probably tell.
EDIT:
I discovered that I was updating the wrong file, I should be updating:
tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg
I figured this out by grepping the flash process for pinmux and .cfg.
Comparing the original file with this name and my new one, I can see I am attempting to change the pinmux register from
pinmux.0x02434090 = 0x00000401; # soc_gpio12_ph0: gp, tristate-disable, input-disable, lpdr-disable
to
pinmux.0x02434090 = 0x00000405; # soc_gpio12_ph0: gp, pull-down, tristate-disable, input-disable, lpdr-disable
However, replacing this file and running a flash again, I only ever see 0x401 at that register. So my change is having no affect. Any reasons as to why would be appreciated!
Am I forgetting some command that I need to run after replacing cfgs?
EDIT 2:
I got the registers to update by doing a full flash. I have been getting some inconsistent update behavior by only flashing the MB1_BCT partition, not sure why.
I can succesfully update the register with the new pinmux.
I think it is at this point that the differences between the Nvidia dev kit and my Seeed brand are getting in the way. They provide a custom pinmux to support their board, so I don’t even know if I can use the pinmux spreadsheet provided by Nvidia.
It is a shame that Nvidia doesn’t sell the OG dev kit anymore, obviously I would have preferred to get that, but instead I had to go with this third party.
Thanks Dave for the help thus far - I will post back here with results so that others can benefit.