No, I am referring to NVGINDEX_EL1 and NVGDATA_EL1 registers where we are using the channels (information/commands) RT_SAFE_MASK, RT_WINDOW_US and RT_FWD_PROGRESS_US mentioned on page 496. Sorry for the wrong terms used before, but I just referred to the email that was sent to us by one of the NVIDIA engineers.
Anyway, the code itself is part of the kernel and there’s no separate binary but below is a snippet of the code we are running on Jetson Xavier:
asm volatile (
"msr $NVGINDEX_EL1, %0 \n"
"msr $NVGDATA_EL1, %1 \n"
:: "r" (80),
“rt_safe_mask” variable is any value between 0-255 ($(NUM_CORES):0 bits) which is passed in through the grub command line. It has been verified that the value passed through the kernel arguments has been passed to code which should have set these values but something in the assembly code itself is failing.
The above code is ported in exactly the same way on DRIVE OS 22.214.171.124 or the previous DRIVE OS.
Similarly, we are updating other registers where NVGINDEX_EL1 is set to 81 or 82. Also, care has been taken to reset RT_SAFE_MASK register before setting other two registers.
Also, there’s no error code displayed in the kern.log or syslog. Dunno if there’s any other log file we should refer to.