Our custom board requires only a single lane of PEX4 (L4) so that we can use the USB3 TX3/RX3 on L7 of the HSIO UPHY, as per the mux diagram in the TRM.
We know how to configure the DTB to assign a single lane of the p2u for PEX4, and to enable the DTB pinmux USB lanes, ports, and connections to the USB controller.
In order to use the USB function on HSIO L7, is it also required to change the MB1 BCT /uphy-lane/lane-owner-map, or the hsio-uphy-config ODMDATA, or will a correct DTB configuration be enough to give a correct UPHY mapping in Linux?
This appears to be possible. If step through ODMDATA values for hsio-uphy-config-#, I can get combinations where either USB3-3 is working or PEX4 is working, so at this point I just need to find one where both are working which will take some time.
It would be helpful if someone could say what the hsio-uhpy-configs map to on tegra234. The HSIO-PCIE XBAR ODMDATA values for tegra194 were documented in platform adaptation guide.
hsio-uphy-config-4 seems to have configured the UPHY in a way that is doing what is required for our board. It would be helpful if you could confirm the mapping of this UPHY config. Maybe there is one better suited for our 1-lane PEX 1 + 1-line PEX 4 + USB superspeed 0 - 3.
That doesn’t answer my question. Can’t you just tell me what the configurations are? I understand it’s not validated, since it’s not possible to try with any devkit.