Hi Nvidia,
I’m testing USB SI.
I followed the document to set compliance test mode.
But it doesn’t work.
The devmem always readback 0x2A0.
Did I have something wrong?
Carrier Board : Custom carrier board
Module : Orin NX 16GB
OS : L4T 35.3.1
wilson@OrinNX:~$ cat /sys/bus/usb/devices/usb1/power/control
on
wilson@OrinNX:~$ cat /sys/bus/usb/devices/usb2/power/control
on
wilson@OrinNX:~$ sudo devmem2 0x03610420 w 0x10340
[sudo] password for wilson:
/dev/mem opened.
Memory mapped at address 0xffff89e72000.
Value at address 0x3610420 (0xffff89e72420): 0x2A0
Written 0x10340; readback 0x2A0
wilson@OrinNX:~$ sudo devmem2 0x03610430 w 0x10340
/dev/mem opened.
Memory mapped at address 0xffffa23e6000.
Value at address 0x3610430 (0xffffa23e6430): 0x2A0
Written 0x10340; readback 0x2A0
wilson@OrinNX:~$ sudo devmem2 0x03610440 w 0x10340
/dev/mem opened.
Memory mapped at address 0xffff9fc5e000.
Value at address 0x3610440 (0xffff9fc5e440): 0x2A0
Written 0x10340; readback 0x2A0
Will the result become different if you use busybox devmem instead of devmem2?
Hi Wayne,
It doesn’t work too.
$ sudo busybox devmem 0x03610420
0x000002A0
$ sudo busybox devmem 0x03610420 32 0x10340
$ sudo busybox devmem 0x03610420
0x000002A0
Hi @Wilson_Lin
As the document note in your screenshot, it also told you cannot readback the value. It seems a expected result.
1 Like
Hi Wayne,
I will try to test again, thanks reply.
There is a USB hub on devkit carrier board. The tuning guide is not for that. Why did you do such test on devkit?
In addition, as you can see the info here: Jetson FAQ | NVIDIA Developer
Jetson Orin NX & Jetson Orin Nano series modules are not pin-compatible with Jetson Xavier NX series modules, but you can design a carrier board for the I/Os they have in common, such that both modules are supported.
Hi @Trumany,
Sorry, it’s my fault.
We use our custom carrier board not Xavier NX developer kit.
The USB3 is from the Orin NX module.
Can you share the schematic of this USB part?
Hi Trumany,
This is our schematic of this USB part.
gbo_USB3 P0 to P2.pdf (180.7 KB)
Hi,
What are U2H1_DM* U2H2_DM* in the schematic? Are they usb Hub?
Please be aware that the test needs to be done on the root hub port. You cannot do it behind external hub.
Yes the usb2 part is connect to usb hub.
We just test the usb3 part.
Could we check the schematic of the usb2 part?
Hi Wayne,
I have a question.
The document step 8~10
It says that connect the RX port. But we just test TX in our team. We don’t have the RX test device.
How can I following the test?
And we connect the TX port and test.
In our test.
The USB3 port 0 and port1 just get CP0 waveform. It’s fail in CP1 check option step.
The USB3 port 2 just get CP0, CP1 waveform. It can finsh the Gen1 5G test but no SSC.
USB3 no SSC
USB3 port0/port1 just CP0
Hi Wilson,
我就直說了, 你的schematic看起來有點問題. 所以我們需要usb2那部份的圖.
今天如果線路圖有問題的狀況下 你後面的compliance也不會過. 所以我們先暫不討論你現在詢問的這些問題
Let me go straight about this. Your schematic seems having proble, so we need the usb2 part schematic.
Under this situation, even some compliance test may not pass later.
請問一下USB2_AP_N/P_L接到哪？
Where is USB2_AP_N/P_L connected to?
It connect to Orin NX pin 121, pin 123
如果我的理解沒錯的話, 你現在所有的usb2.0 pin全部都是USB2_D_P/N接出來之後過了一個usb2 hub再外接給你後面的介面是嗎?
If I understand it correctly, then all the usb2.0 pins on your board are from a usb2 hub which is connected to USB2_D_P/N pin?
