USB can't set compliance test mode

對, 這種設計是錯的. 我們沒辦法同時一個usb2 pin控制多個界面

Yes, such design is wrong. Our usb pin cannot control multiple interfaces.

感謝,我會再和我們HW RD確認。Thanks very much.

Hi @WayneWWW ,

再請問一下,已知Orin NX USB2 有3 port,
USB Type A的pin是USB3 + USB2 pin,
所以NV的設計上如果USB 3 type A是否只能搭配原生的USB2? 這樣USB2 的port不會不夠用嗎?

You can use same USB HUB for both USB2 and USB3. Please refer to below info from FAQ topic.

Q5: Can use2.0 port from a hub combine with USBSS port directly?

One USB2 roothub cannot be paired with multiple USB3 roothubs. Valid design is one USB2 roothub + one USB3 roothub like:

*) USB2 + USB3 in pair connecting to a USB HUB

*) USB2 + USB3 in pair connecting to a PD controller and then to a type-C port

*) USB2 + USB3 in pair connecting to a type-A port

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Hi @Trumany,

Thanks the reply.
如果我將USB2訊號斷開,是否能測試USB3 SI pattern?

We don’t support other port design than what are mentioned above. And so the SI test like you said is not supported either.


We want to check our test step is right.
We set the following command and test two devices.

And we connect USB to the SI test scope and start testing.

  1. Orin NX 16 GB module + Xvier NX Devkit Carrier Board + L4T35.3.1

    1. 4 Port USB3 Type A
      We can’t get the signal from the DUT.
  2. Orin Nano 8GB Developer Kit + L4T35.3.1

    1. 4 Port USB3 Type A
      We can’t get the signal from the DUT.
    2. Tpye C USB
      It can get CP0 signal but can’t get CP1.

There is USB HUB on devkit board, you can not do compliance test like that. Please refer to this topic: For any compliance that is going through an external hub, please contact the hub vendor for the tool.

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The test steps in guide are surely correct, you have no need to validate that as that has been verified. You only need to use that on correct USB combination like said previously.

Hi @Trumany
Yes we’re sure the tuning guide is correct. We’re just worried that we’ve misunderstood the test instructions on the documentation.
Because the test of type C on the Orin Nano Developer Kit is failed too. (It’s USB2 + USB3 in pair connecting to a PD controller and then to a type-C port like above)
This means that we have misunderstood the test method on the document. Please help us and point out where we misunderstood.

Have you confirmed your fixture is correctly plugged into DUT? Since there is switch of type-c port on devkit, you should confirm if it is correctly set first. You can refer to the P3768 schematic for detail.

Hello Sir

I have checked the type C topology of Orin nano kit. The USB resource are USB3.2 Port1 and USB2.0 port0.
Becasue of the Mux has a pull down resistor on SEL pin, it means A short to B.

At this situation, USB3.2 port1 is connecting diretly on positive or negative side in Type C!

I may measure the USB3.2 Port1 pattern on positive or negative side,right?

Hello Wayne

您的意思是,NV USB3+USB2,Type A的組合,必須是:
(1)原生USB3+ 原生USB2


NV Orin_NX/Nano依datasheet指出,

請問原生USB3 + 原生USB2的組態,有限制嗎?
For example:
必須USB3.2 port0 + USB2.0 port0 ?

USB3.2 port0 + USB2.0 Port2

Hello Sir

Do you have any update about the Orin_NX oringinal USB3.2 port1/2/3 compliance test??
We followed the document , but it still can not work. I have marked the steps we did ,but it just could go to Step6 !And we stuck or could not go down to Step 7/8/9.

Please tell us how to do it. Thank you!!!

What a strange problem!
The oringinal USB3.2 signals can not to compliance test by the SOP !!!
Jetson_Orin_NX_Series_Orin_Nano_Series_Tuning_Complinace_Guide_DA-11267-001_v0.9.pdf (1.1 MB)


Hi, as said the test steps are correct. You have got CP0 output on typc c port. Step 8 and step 9 in the tuning guide shall cover the CP1 case.

  1. Connect RX± to external Ping.LFPS (20 MHz frequency; two periods) signal generator.
  2. Sending a Ping.LFPS to the RX port of the DUT in compliance state will cause the compliance pattern to transition to the next one. Contact generator vendor for support to provide required number of Ping.LFPS until controller pumps out the required compliance pattern.

Hi Trumany,

We connect the RX± and it can get CP1. Thanks a lot.
But we can’t get SSC in test.
I know the PCIE is not supported SSC yet in document.
Is the USB3 is not supported SSC too?

Had you applied the patch of 0001-disabling-the-spread-Spectrum.patch? If had, it will disable SSC of USBSS too, as PLLE is shared between USB and PCIE. Once PLLE SSC is enabled/disabled, it affects both PCIE and USB. By default, PLLE SSC is enabled.

We didn’t apply the patch of 0001-disabling-the-spread-Spectrum.patch. But still can’t get SSC.
How can I check SSC is enable or disable in Ubuntu?

We are checking this internally, will update once available.