USB issue

[dimaz]

    Hello.

We made our own carrier board with modified USB.
We use USB 3.1 as usual USB2.0 (USBSS lanes are not connected).

Moreover, we excluded RTS5489-GR chip from our schematic.

As a result -USB doesn’t work correctly:

[  275.634166] usb usb1-port2: disabled by hub (EMI?), re-enabling...
[  275.634463] usb 1-2: USB disconnect, device number 8
[  275.957869] usb 1-2: new high-speed USB device number 9 using tegra-xusb
[  275.978902] usb 1-2: New USB device found, idVendor=0781, idProduct=558a
[  275.978913] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[  275.978920] usb 1-2: Product: Ultra
[  275.978932] usb 1-2: Manufacturer: SanDisk
[  275.978938] usb 1-2: SerialNumber: 4C530001110415114045
[  275.980000] usb-storage 1-2:1.0: USB Mass Storage device detected
[  275.980529] scsi host0: usb-storage 1-2:1.0
[  276.988338] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra            1.00 PQ: 0 ANSI: 6
[  276.993084] sd 0:0:0:0: [sda] 60062500 512-byte logical blocks: (30.8 GB/28.6 GiB)
[  276.994554] sd 0:0:0:0: [sda] Write Protect is off
[  276.994688] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
[  276.995328] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or F
UA[ 1418.506454] usb 1-2: Device not responding to setup address.

[  277.002512]  sda: sda1
[  277.004874] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 1044.855165] usb usb1-port2: disabled by hub (EMI?), re-enabling...

USB disabled by hub and re-enabling in a cycle.

What can be a reason of it?
Can device work correctly without RTS5489-GR hub chip?
Do I have to make changes inside device tree?

Thank you in advance!

[DaneLLL]

Hi,
By default it is type-A USB3 port and yours is USB2 port. Please modify th edevice tree accordingly. There is guidance in adaptation guide. Also after the modification, please run compliance test to fine tune the signals. The default setting is for developer kit.

[dimaz]

Hi DaneLLL.
According to the document Jetson_Xavier_NX_Tuning_and_Compliance_Guide_Application_Note_DA-09890-001_v1.2.pdf:

Could you please provide me this software?

[dimaz]

So, how to add offset?

[Trumany]

As said in guide, devmem2 is the tool to w/r register.

[dimaz]

According to guide.
There is register FUSE_USB_CALIB (Address 0x038201F0)
It contains HS_CURR_LEVEL field.

If modification to HS_CURR_LEVEL is necessary, it must be done as an offset to the default
fused value to account for silicon process differences.

CAUTION: Do not apply a global overwrite HS_CURR_LEVEL value for all silicon. There is a
mechanism provided in software to read fuse USB drive strength and add an offset to it.
Consult NVIDIA SWPM/CE for additional information.

So, my question is how to apply offset to the FUSE_USB_CALIB value?
Do I have to calculate new HS_CURR_LEVEL value and rewrite it to 0x038201F0 register?

[Trumany]

As you can see in the guide as below:

HS_CURR_LEVEL Offset Adjustment Procedure
If the default value does not fit customer design, adjust the HS_CURR_LEVEL register in order to pass the USB HS eye diagram.
Follow this procedure:

1. Obtain default value; read register FUSE_USB_CALIB (Address 0x038201F0)
   a). USSB_CALIB[5:0] USB pad HS_CURR_LEVEL[5:0] for Port 0
   b). USSB_CALIB[16:11] USB pad HS_CURR_LEVEL[5:0] for Port 1
   c). USSB_CALIB[22:17] USB pad HS_CURR_LEVEL[5:0] for Port 2
2. Calculate the offset from fused HS_CURR_LEVEL value and desired value to pass eye mask.
   a). For example, if default value is 0x20 and desired value is 0x1C, then offset = -4
   b). For example, if default value is 0x10 and desired value is 0x14, then offset = +4
3. Adjust HS_CURR_LEVEL register as described in the “Tuning Procedure” section (Note: maximum allowable offset: +/-6 steps).
4. Provide the “tuned offset value” to software team
   Software Verification
   NVIDIA recommends a functional check. Connect the DUT to USB hosts and devices to perform a check on functionality.
   To check if software has implemented the tuned offset step properly, load new software with offset included into another DUT and check to ensure:
   HS_CURR_LEVEL = USB_CALIB + tuned offset steps

[dimaz]

@Trumany

Provide the “tuned offset value” to software team

How does it work?
Do I have to provide these values to NVIDIA software team?
And how to implement new values to image sources?

[WayneWWW]

The tune values are stored inside the device tree and it is open source. You can modify it to match your tuning parameters.

[dimaz]

Could you please hint me the file name, where this value is stored?

[DaneLLL]

Hi,
Please modify like this:

        xusb_padctl: xusb_padctl@3520000 {
                status = "okay";

                pads {
                        usb2 {
                                lanes {
                                        usb2-0 {
+                                               nvidia,hs_curr_level_offset = <6>;
                                                nvidia,function = "xusb";
                                                status = "okay";
                                        };
                                        usb2-1 {
+                                               nvidia,hs_curr_level_offset = <6>;
                                                nvidia,function = "xusb";
                                                status = "okay";
                                        };
                                        usb2-2 {
+                                               nvidia,hs_curr_level_offset = <6>;
                                                nvidia,function = "xusb";
                                                status = "okay";
                                        };
                                };
                        };