USB OTG device controller operation on TEGRA K1


I have been wrestling with getting the USB OTG device controller to make transactions. This particular implementation uses a custom OS from TFTP boot so the Linux drivers and such does not apply.

The situation is:

  • set the ASYNCLISTADDR_0 to the dQH array and set the controller to run
  • initial setup packet is received on dQH[0] for get device descriptor from host
  • setup dTDs for data TX (descriptor data), data RX (read of 0 to complete the transaction)
  • set the dTD next on dQH[0] and dQH[1]
  • prime ENDPTPRIME_0

Looking in memory, it seems the controller is not processing the dTDs on dQH[0] and dQH[1]

The USB bus analyzer shows in this order:

  • NAK for IN (device to host)
  • get descriptor
    • setup packet is ACK
    • NAK for data phase

I have tried all the little tiny bits of the programming guide… it makes little sense. So my questions for NVIDIA support are:

  • after the reset button is pressed and the TFTP boot… the registers seems to show a working OTG device controller, this has all been setup by boot ROM as discussed in the programming manual. Is this correct? If so, does this mean I do not need to program any of the PLL, UTMIP registers as stated in the manual? I have tried the items in the programming guideline… it makes no difference.

  • why does the device controller NAK on endpoint 0 IN (device->host) when there are no transfers posted to qTDs?

  • does NVIDIA have a working demo program to illustrate the setup necessary to get the USB OTG device controller working with valid transactions?

  • where can I get support for this USB OTG controller?

Thank you very much for your time.


Okay got it working. The issue was the bit 1 was asserted on the next dTD pointer of the dQH. So, in short, all that configuration mentioned in the manual is already done by BOOT ROM :)