关于USB3.0布线线距有问题，我在这篇文档中关于pair-pair间距要求是4x/3x的单位不明确，dielectric指的是线宽么？
Dielectric is the material between copper layers; the distance between trace and adjacent reference plane. They recommend you space TX and RX pairs 4x or 3x dielectric apart.
tanks your reply！
I want to know the differential signal trace spacing about usb3.0 and pcie？ i.e PCIE0_TX1_N and PCIE0_TX1_P
What do you mean? As said, it depends on your PCB board stack-up as the space is based on dielectric. If you mean the space b/w TX/RX, it is as below info.
TX and RX should not be routed on the same layer. If this is required in a design, they should not be interleaved, and the spacing between the closest RX and TX lanes must be 9x Dielectric height spacing.
