Our team is currently working on using an Orin NX module with a PCIE peripheral that requires SRNS. From brief research, it appears that the required modifications to enable SRNS are to disable SSC (Spread Spectrum) in the BPMP device-tree, and then use the “nvidia,enable-srns” device-tree binding for the kernel device-tree. The below snippets show the changes made to the BPMP device-tree.
clock@plle {
clk-id = <0x64>;
disable-spread = <1>; // Have tried this binding
};
Originally, the clocks that we’re modified were “nvhs” and “gbe”, but after researching on the AGX forums, I found the Orin NX does not have the “nvhs” PHY, and the “gbe” phy between Orin NX and AGX vary greatly. I then found mention of the “plle” clock, which I assumed to belong to the “hsi0” phy.
I’m looking for a nice set of concrete steps to enable SRNS on CN4 for Orin NX. If the hardware is not capable, I am looking for an NVIDIA representative to explicitly say so.
When you say that, you mean with regard to the Orin NX correct? The Orin AGX seems to have documentation indicating that SRNS is possible on the NVHS UPHY.
We needed SRNS on C4 for our prototype. You’re correct that the plle clock needs to have spread spectrum disabled for C4. The following works in R36.3:
@nvidia_user_1234 - please don’t remove this functionality. I know it isn’t a production solution, but it is very useful for prototyping - in our case we are unable to easily route a common PCIe clock to the downstream device, which is attached to the prototype using off-the-shelf cables and adapters.