Use the PCIe on TX2 NX

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hi,

If I want to use the 1x PCIe on TX2 NX module, where the settings in the device tree?

Thanks.

3

What pcie x1? Which pin?

4

The pins are 167, 169, 172, 174,173, 175.

Thanks.

5

No software change should be included. By default it is already enabled.

6

The boot messages about pcie showed as below:

:~$ dmesg | grep pcie
[ 0.442734] iommu: Adding device 10003000.pcie-controller to group 48
[ 0.442749] arm-smmu: forcing sodev map for 10003000.pcie-controller
[ 0.928860] tegra-pcie 10003000.pcie-controller: 2x1, 1x1, 1x1 configuration
[ 0.929583] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.929868] tegra-pcie 10003000.pcie-controller: probing port 0, using 2 lanes
[ 0.932083] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 1.405741] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 1.788499] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 2.190635] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 2.192654] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 2.593593] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 2.997872] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 3.402135] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 3.404152] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 3.608510] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 3.608723] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails

My PCIe device is a FPGA chip. We have tried this schema on Xavier NX board. And add some delays in function “tegra_pcie_dw_host_init” in the pcie-tegra.c like what we done on the Xavier board. But it seems it won’t work.

Any help?

Thanks.

7

tegra_pcie_dw_host_init is for Xavier. TX2-NX is T186 SoC. Not using this driver.

You can try to unbind/rebind or rescan it first.

8

Yes, we found that, the function will never be executed.

  1. Are there any other method (modify the driver code) to implement this like on Xavier?
  2. How to unbind/rebind or rescan it? Are there any worked examples?

Thanks.

9

please try this.

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 0a5b27e72371..952e7fe60d9b 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2537,6 +2537,7 @@ static void tegra_pcie_check_ports(struct tegra_pcie *pcie)
                dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
                tegra_pcie_port_disable(port);
        }
+       msleep(1000);
        /* configure all links to gen2 speed by default */
        tegra_pcie_link_speed(pcie);
        if (pcie->soc_data->mbist_war)
10

Thanks for the quick reply :).

We will try the code. And I’m also glad to know how to rescan it without coding. May you give some clues? We’ve tried rescan it after booting up, but failed. So we have to go to modify the driver code.

Thanks.

11

It should be something like

echo 1 > /sys/bus/pci/devices/0004:00:00.0/rescan

You may need to replace the devices here to match yours.

12

After reset once, the dmesg shows:

dmesg | grep pcie
[ 0.445637] iommu: Adding device 10003000.pcie-controller to group 48
[ 0.445652] arm-smmu: forcing sodev map for 10003000.pcie-controller
[ 0.943273] tegra-pcie 10003000.pcie-controller: 2x1, 1x1, 1x1 configuration
[ 0.943982] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 0.944269] tegra-pcie 10003000.pcie-controller: probing port 0, using 2 lanes
[ 0.946577] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 1.369069] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 1.771620] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 2.174518] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 2.176537] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 2.282680] tegra-pcie 10003000.pcie-controller: PCI host bridge to bus 0000:00
[ 2.292896] pcieport 0000:00:03.0: Signaling PME through PCIe PME interrupt
[ 2.292907] pcie_pme 0000:00:03.0:pcie001: service driver pcie_pme loaded
[ 2.293003] aer 0000:00:03.0:pcie002: service driver aer loaded

So, for my device should it be

/sys/bus/pci/devices/0000:00:03.0/rescan

Right?

Thanks.

13

Is this still an issue to support? Any result can be shared? Thanks