# Using GPIO as an IRQ line **URL:** \ **Category:** Jetson TK1\ **Created:** [April 27, 2016, 5:44pm UTC](https://forums.developer.nvidia.com/t/using-gpio-as-an-irq-line/42516 "2016-04-27T17:44:07Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![John\_PrizmLabs](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@John\_PrizmLabs](https://forums.developer.nvidia.com/u/John_PrizmLabs)\ **Post date:** [April 27, 2016, 5:44pm UTC](https://forums.developer.nvidia.com/t/using-gpio-as-an-irq-line/42516/1 "2016-04-27T17:44:07Z")
Hello, I am trying to use gpio 160 (GPIO\_PU0) as the IRQ for a device driver, which maps to physical pin 40 on J3A2. I think the driver is having issues related to interrupt handling. The kernel logs show it is requesting IRQ 337. Does anyone know how I can verify that GPIO\_PU0 maps to the IRQ number 337? I have the Technical Reference Manual but don’t see anything related to IRQ under 8.12.38 PINMUX\_AUX\_GPIO\_PU0\_0. ---
**Author:** ![Trumany](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/trumany/32/14043_2.png) [@Trumany](https://forums.developer.nvidia.com/u/Trumany)\ **Post date:** [April 29, 2016, 3:33am UTC](https://forums.developer.nvidia.com/t/using-gpio-as-an-irq-line/42516/2 "2016-04-29T03:33:01Z")
How to enable GPIO\_PU0 interrupt is described in 8.11, not related to PINMUX\_AUX\_GPIO\_PU0, could you please post the logs of requesting IRQ 337 here? Thanks. ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [May 4, 2016, 9:19am UTC](https://forums.developer.nvidia.com/t/using-gpio-as-an-irq-line/42516/3 "2016-05-04T09:19:31Z")
Hello, John\_PrizmLabs: You can check the function ‘gpio\_to\_irq’ in kernel source code for reference. br ChenJian