Using spidev to display data sent from FPGA master board on the jetson Xavier agx set as slave

Hello,

I am trying to figure out how to

  1. Set up the Jetson Xavier as a slave, I saw on other forums I would need to modify the device tree file, but I do not have access to it.
  2. display the 16bit data I am sending from the master (FPGA) on the Jetson Xavier AGX board terminal
  3. I have tested a simple python code for the Jetson loopback test, however, I am not getting a clock produced from the board as well as while checking using the oscilloscope.

Code I am using to receive from FPGA

import spidev
import time
spi = spidev.SpiDev(0, 1)
spi.max_speed_hz = 7000000
spi.bits_per_word = 16
spi.mode = 0

try:
while True:

	a = spi.readbytes(16) 
	time.sleep(0.1) 
	print(a)

finally:
spi.close()

  1. Using jetson-io to configure the PINS
  2. Reference to below topic for device tree modification.
    How to set to spi slave mode - #11 by ShaneCCC

Thanks

Thanks for the link, I have updated the device tree to have SPI@3210000 set as slave, However How can I receive the data from the FPGA, I tried a python code using spidev library but I keep getting errors.

import spidev
import time
spi = spidev.SpiDev(0, 1)
spi.max_speed_hz = 7000000
spi.bits_per_word = 16
spi.mode = 0

try:
while True:

	a = spi.readbytes(16) 
	time.sleep(0.1) 
	print(a)


finally:
spi.close()

OSError: [Errno 5] Input/Output error.

Should FPGA send data to Jetson SPI slave mode.
Have reference to below relative topic.

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