V4l2-ctl failed with “VIFALC_TDSTATE”

Jetpack Version:

5.1.1

Hardware:

camera==>max9295=====>max96712====>Orin NX 16G

max96712 output:

4-Lane
Continuous clock
Data rate=1400Mbps
4x1920x1280@30 fps(vc0~vc3), yuv422(UYVY) 8bit

device tree:


1. vi config

tegra-capture-vi {
                num-channels = <8>;
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        vi_port0: port@0 {
                                reg = <0>;
                                yuv_vi_in0: endpoint {
                                        vc-id = <0>;
                                        port-index = <0>;
                                        bus-width = <4>;
                                        remote-endpoint = <&yuv_csi_out0>;
                                };
                        };
                ....
               };
       };

2. csi config

nvcsi@15a00000 {
                        num-channels = <8>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        csi_chan0: channel@0 {
                                reg = <0>;
                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        csi_chan0_port0: port@0 {
                                                reg = <0>;
                                                yuv_csi_in0: endpoint@0 {
                                                        port-index = <0>;
                                                        bus-width = <4>;
                                                        remote-endpoint = <&yuv_yuv_out0>;
                                                };
                                        };
                                        csi_chan0_port1: port@1 {
                                                reg = <1>;
                                                yuv_csi_out0: endpoint@1 {
                                                        remote-endpoint = <&yuv_vi_in0>;
                                                };
                                        };
                                };
                        };
               .....
             };

3.mode config
                        mode0 {
                                mclk_khz = "24000";
                                num_lanes = "4";
                                tegra_sinterface = "serial_a";
                                phy_mode = "DPHY";
                                vc_id = "0";
                                discontinuous_clk = "no";
                                dpcm_enable = "false";
                                cil_settletime = "0";
                                lane_polarity = "6";
                                csi_pixel_bit_depth = "16";
                                pixel_t = "yuv_uyvy16";

                                active_w = "1920";
                                active_h = "1280";
                                readout_orientation = "0";
                                line_length = "2200";
                                inherent_gain = "1";
                                pix_clk_hz = "108000000";
                                serdes_pix_clk_hz = "350000000";

                                gain_factor = "10";
                                min_gain_val = "0"; /* dB */
                                max_gain_val = "300"; /* dB */
                                step_gain_val = "3"; /* 0.3 */
                                default_gain = "0";
                                min_hdr_ratio = "1";
                                max_hdr_ratio = "1";
                                framerate_factor = "1000000";
                                min_framerate = "30000000";
                                max_framerate = "30000000";
                                step_framerate = "1";
                                default_framerate = "30000000";
                                exposure_factor = "1000000";
                                min_exp_time = "59"; /*us, 2 lines*/
                                max_exp_time = "33333";
                                step_exp_time = "1";
                                default_exp_time = "33333";/* us */
                                embedded_metadata_height = "0";
                        };


For the same config, We can get correct data on Orin 32GB., but failed for Orin NX/Orin Nano.

kernel msg:

[ 1817.086023] bwmgr API not supported
[ 1821.125974] bwmgr API not supported
[ 1823.639687] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[ 1823.652432] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 1823.662590] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 1823.670324] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[ 1823.681001] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 1823.688725] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 3
[ 1823.699476] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

trace log:

root@tegra-ubuntu:/home/nvidia# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 25/25   #P:4
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
 vi-output, yuv_-2506    [003] ....    54.549332: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1280 fmt 13
     kworker/2:5-150     [002] ....    54.588765: rtcpu_vinotify_event: tstamp:2436758160 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:77974644160 data:0x719d580010000000
     kworker/2:5-150     [002] ....    54.588767: rtcpu_vinotify_event: tstamp:2436758298 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:77974686816 data:0x0000000031000001
     kworker/2:5-150     [002] ....    54.588767: rtcpu_vinotify_event: tstamp:2436758458 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:77974704480 data:0x719d550010000000
     kworker/2:5-150     [002] ....    54.588767: rtcpu_vinotify_event: tstamp:2436758592 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:77974764800 data:0x0000000031000002
 vi-output, yuv_-2506    [003] ....    57.365315: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1280 fmt 13
     kworker/2:5-150     [002] ....    57.396639: rtcpu_vinotify_event: tstamp:2525192547 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:80790611168 data:0x719d580010000000
     kworker/2:5-150     [002] ....    57.396641: rtcpu_vinotify_event: tstamp:2525192701 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:80790653856 data:0x0000000031000001
     kworker/2:5-150     [002] ....    57.396641: rtcpu_vinotify_event: tstamp:2525192855 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:80790671456 data:0x719d550010000000
     kworker/2:5-150     [002] ....    57.396641: rtcpu_vinotify_event: tstamp:2525192989 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:80790731840 data:0x0000000031000002
 vi-output, yuv_-2506    [003] ....    60.180315: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1280 fmt 13
     kworker/2:5-150     [002] ....    60.200511: rtcpu_vinotify_event: tstamp:2613084205 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:83605609952 data:0x719d580010000000
     kworker/2:5-150     [002] ....    60.200512: rtcpu_vinotify_event: tstamp:2613084346 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:83605652608 data:0x0000000031000001
     kworker/2:5-150     [002] ....    60.200513: rtcpu_vinotify_event: tstamp:2613084505 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:83605670240 data:0x719d550010000000
     kworker/2:5-150     [002] ....    60.200513: rtcpu_vinotify_event: tstamp:2613084638 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:83605730592 data:0x0000000031000002
 vi-output, yuv_-2506    [003] ....    62.996303: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1280 fmt 13
     kworker/2:5-150     [002] ....    63.000387: rtcpu_vinotify_event: tstamp:2700680468 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:86421568000 data:0x719d580010000000
     kworker/2:5-150     [002] ....    63.000388: rtcpu_vinotify_event: tstamp:2700680607 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:86421610656 data:0x0000000031000001
     kworker/2:5-150     [002] ....    63.000388: rtcpu_vinotify_event: tstamp:2700680763 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:86421628320 data:0x719d550010000000
     kworker/2:5-150     [002] ....    63.000389: rtcpu_vinotify_event: tstamp:2700680899 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:86421688704 data:0x0000000031000002
 vi-output, yuv_-2506    [003] ....    65.812327: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1280 fmt 13
     kworker/2:5-150     [002] ....    65.816201: rtcpu_vinotify_event: tstamp:2788704522 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:89237607104 data:0x719d580010000000
     kworker/2:5-150     [002] ....    65.816202: rtcpu_vinotify_event: tstamp:2788704660 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:89237649760 data:0x0000000031000001
     kworker/2:5-150     [002] ....    65.816202: rtcpu_vinotify_event: tstamp:2788704816 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:89237667456 data:0x719d550010000000
     kworker/2:5-150     [002] ....    65.816202: rtcpu_vinotify_event: tstamp:2788704949 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:89237727808 data:0x0000000031000002

hello cloundliu,

since you’re working with Orin NX,
please aware that CSI0 D1 and CSI1 D0 P/N will always been swizzled for P/N.

hence, please have a try to configure lane_polarity.
you may see-also reference driver, $public_sources/kernel_src/hardware/nvidia/platform/t23x/p3768/kernel-dts/cvb/tegra234-camera-rbpcv2-imx219.dtsi

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