What are best way for disable Jetson TX1 PCIe SSC ?

There tried to disable PCIe SSC which only disable Kernel codes seems no influence.
Follow Spec 5.2.17 flag PLLE_SSCBYP found out uboot source code.
To mask clock.c “PLLE_SS_CNTL_SSCINC” relation codes that SSC seems be disabled (follow Source code changed:to show change points).
But can’t be sured those way are correct and will no make any side event .
Hope the nVidia TX1 experts suggest us which best way for disable PCIe SSC.

Idea source:

Document: Tegra_X1_TRM_DP07225001_v1.2p.pdf
Register: 5.2.17 CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
Flage: PLLE_SSCBYP: 0 enables spreading, 1 disables spreading

Source code changed:

#if 0 // mask PLLE_SSCBYP flag to disable PCIe Spread Spectrum Clock(SSC)
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
value &= ~PLLE_SS_CNTL_SSCINC(0xff);
value |= PLLE_SS_CNTL_SSCINC(1);
value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
value |= PLLE_SS_CNTL_SSCMAX(0x21);
value &= ~PLLE_SS_CNTL_SSCINVERT;
value &= ~PLLE_SS_CNTL_SSCCENTER;
value &= ~PLLE_SS_CNTL_BYPASS_SS;
value &= ~PLLE_SS_CNTL_SSCBYP;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);

/* 6. Wait 300 ns */

udelay(1);
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);

#endif

Can you please give release info? Is it R28.1 or R28.2?

If it is R28.2, please use the following patch to disable spread

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 80ca8de05005..ff4365fd7e81 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2252,7 +2252,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
     if (ret < 0)
         goto out;

-    if (pll->params->ssc_ctrl_reg != PLLE_SS_CTRL)
+    //if (pll->params->ssc_ctrl_reg != PLLE_SS_CTRL)
         goto out;

     val = pll_readl(PLLE_SS_CTRL, pll);

Thank for your reply:
Our source code base were used JetPack-L4T-2.3.1-linux-x64.run to install development environment.
Those L4T BSP information was R28.1. I am check can’t find code static int clk_plle_tegra210_enable(struct clk_hw *hw) on our code.
Could you teach us how to disable SSC on R28.1 .

Please use the following patch to disable spread in R28.1

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b05221e34f60..f989a437c23a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2216,6 +2216,8 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
     if (ret < 0)
         goto out;
 
+    goto out;
+
     val = pll_readl(PLLE_SS_CTRL, pll);
     val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
     val &= ~PLLE_SS_COEFFICIENTS_MASK;