I checked the tegra manual, because I couldn’t find the Nano jetson TRM https://docs.nvidia.com/jetson/l4t/#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html# and I also checked the ARM TRM of the Nano Jetson processor https://www.ee.ryerson.ca/~courses/coe838/Data-Sheets/Cortex_A57_MPcore.pdf but in neither document could I find the clock drift? I need to know in x time say a year how much will the clock have drifted compared to TAI?
Please check the TX1 TRM
As usual a totally useless answer. Just to satisfy some answer metric I guess. Have you actually checked the TX1 TRM? It doesn’t contain anything about the clock drift and 15 occurrences of the word drift, but none about clock drift. It’s mostly temperature drift. Also stop make me work for you by having to label your stupid data every time I want to log in, stupid scammers. Go to mechanical turk or hire people to label your shitty data, instead of asking your customers to label your data.
I found this in TX1 TRM
CHAPTER 11: REAL-TIME CLOCK
The Real-Time Clock (RTC) module maintains seconds and milliseconds counters, and five alarm registers. The RTC is in the
‘always-on’ power domain, allowing for the counters to run and alarms to trigger when the system is in low-power state. If
configured, interrupts triggered by the RTC can cause the system to wake up from a low-power state.
• 10-bit milliseconds counter that runs off of a 32.768 kHz clock source.
• 32-bit seconds counter that increment for every 1000 milliseconds.
• Alarm feature that triggers an interrupt when the specified value matches the milliseconds counter.
• Alarm feature that triggers an interrupt when the specified value matches the seconds counter.
• Count-down alarm feature that triggers an alarm after counting down the specified number of seconds.
• Count-down alarm feature that triggers an alarm after counting down the specified number of milliseconds.
• Security bit that disables further processor writes to the seconds counter and ensures that the RTC clock keeps
• Hardware adjusts drift in clock which can occur due to PPM variations in oscillator output.
So how does that answer my question? I need to know what the clock drift will be compared to TAI after a year. There is nothing in that section about clock drift…
The clock drift could be depend on the crystal.
And the freq tolerance of crystal is +/- 20ppm@25C