What is the csr base address of msi on Endpoint side?

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
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1

Hello,
I had a custom carrier board for Nvidia AGX Xavier Module. Kernel version is r35.4.1. My board is an endpoint board and currentle I have a good pcie communication with root board. I am looking for csr base address for msi settings to use during allocation and free operations. Can you please help me?
Best Regards

3

Can anyone from Nvidia reply to my question?
I am developing allocating msi domain. For write and read operations, I need an msi register to write and read msi specific registers as shown below;

static inline void msi_writel(struct pcie_epf_dma *epfnv, const u32 value,
const u32 reg)
{
writel_relaxed(value, epfnv->csr_base + reg);
}

static inline u32 msi_readl(struct pcie_epf_dma *epfnv, const u32 reg)
{
return readl_relaxed(epfnv->csr_base + reg);
}

5

Sorry for the late response.
Is this still an issue to support? Any result can be shared?

6

Yes, still looking for a solution. I am developing an MSI domain codes, and I am looking for a way to reach MSI registers.