What is the Link Control 2 and Link Status 2 Registers Address

  1. What is the Link Control 2 and Link Status 2 Registers Address? This register is in 34.5.5.13 T_PCIE2_RP_LINK_CONTROL_STATUS_2 of Parker TRM and I would like to enable bit4 to make TX2 to enter compliance mode.
  2. Could TX2 enter PCIe test mode by enable bit4 of Link Control 2 and Link Status 2 Registers?

Hi ansonjh, please refer to this topic for related info: https://devtalk.nvidia.com/default/topic/1025493/?comment=5215771. All we currently can provide are in download center.

Hi Trumany,

I know there is no other guide line for SI testing so I try to find the relative register/setting for SI testing by myself. The topic you provided is not useful for us.
I just want to know the address of Link Control 2 and Link Status 2 Registers. If I know the address than I can try to test the PCIe SI. Could you tell me what is the address of Link Control 2 and Link Status 2 Registers?

Hi, as you can see in Table 2 of TRM, the base address of PCIE_ROOT_PORT* are listed, you can add the offset to them to get the address of T_PCIE2_RP_LINK_CONTROL_STATUS_2_*, for example, if it is PORT0, then the base address is 0x10000000, the offset is 0xB0, so the address of T_PCIE2_RP_LINK_CONTROL_STATUS_2_0 is 100000b0.