# What is the relationship between block\_idx and sm\_idx **URL:** \ **Category:** CUDA Programming and Performance\ **Created:** [September 29, 2023, 1:30pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991 "2023-09-29T13:30:01Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![Shaquille](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@Shaquille](https://forums.developer.nvidia.com/u/Shaquille)\ **Post date:** [September 29, 2023, 1:30pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/1 "2023-09-29T13:30:01Z")
Hello, nv experts I didn’t find reference description for the mapping relationship between block\_idx(thread block) and sm\_idx(SM) in nvidia public documents。 I want to know what is the mapping formular, is there anyone would like to teach me? ---
**Author:** ![Robert\_Crovella](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/robert_crovella/32/14043_2.png) [@Robert\_Crovella](https://forums.developer.nvidia.com/u/Robert_Crovella)\ **Post date:** [September 29, 2023, 1:55pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/2 "2023-09-29T13:55:55Z")
There is no relationship or mapping formula prescribed by CUDA. That is why you can’t find any information about it. For many typical CUDA programs, the relationship should be irrelevant anyway. You can study nearly all [the CUDA sample codes](https://github.com/NVIDIA/cuda-samples) and they don’t need the SM ID for any reason. ---
**Author:** ![Shaquille](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@Shaquille](https://forums.developer.nvidia.com/u/Shaquille)\ **Post date:** [September 29, 2023, 2:42pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/3 "2023-09-29T14:42:23Z")
> [@Robert\_Crovella](#): > > For many typical CUDA programs, the relationship should be irrelevant anyway. You can study nearly all [the CUDA sample codes](https://github.com/NVIDIA/cuda-samples) and they don’t need the SM ID for any reason I’m very confused it, because I didn’t find any reference descriptions in nvidia public document, but, I found there must be a fixed mapping formular after I reading this paper:\, it is published by nvidia, and this idea has been merged in cutlass. at the same time, it show this figure: ![1695998427(1)](https://global.discourse-cdn.com/nvidia/original/4X/7/b/7/7b71668aef57a5b957953d213d23cea211922a1c.png) obviously, the author think there is a fixed relationship between CTA and SM, but It still didn’t show the relationship between CTA and SM, I still cannot find this mapping formula in this paper. So, I’m very confused. ---
**Author:** ![striker159](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@striker159](https://forums.developer.nvidia.com/u/striker159)\ **Post date:** [September 29, 2023, 3:14pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/4 "2023-09-29T15:14:16Z")
Using an atomic counter, one can logically reorder blocks such that blocks which are scheduled first have a smaller logical block id ---
**Author:** ![Robert\_Crovella](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/robert_crovella/32/14043_2.png) [@Robert\_Crovella](https://forums.developer.nvidia.com/u/Robert_Crovella)\ **Post date:** [September 29, 2023, 9:17pm UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/5 "2023-09-29T21:17:46Z")
If you want to do this level of tuning, a threadblock can query its SM ID and organize its work that way. For example if you launching a kernel with enough threadblocks to fill a GPU, then each threadblock can query its SM ID, and then choose to do a portion of the work based on SM ID rather than using built-in threadblock variables. This, for example, would allow you to arrange work so as to provide benefit from the L1 cache to multiple threadblocks. If you have multiple threadblocks per SM, you still need to sort out which is which perhaps using a per-SM atomic like what striker159 suggested. You can query the sm id like [this](https://forums.developer.nvidia.com/t/any-way-to-know-on-which-sm-a-thread-is-running/19974/8). [Here](https://stackoverflow.com/questions/59109845/memory-allocation-and-indexing-tied-to-sm-core-in-cuda/59110744#59110744) is an example of a code that does SM-specialization, and allows for multiple blocks per SM. There are a variety of other code examples that do various things based on the SM ID. Here are some examples: [1](https://stackoverflow.com/questions/30361459/what-is-the-behavior-of-thread-block-scheduling-to-specific-sms-after-cuda-kern/30379454#30379454)[2](https://stackoverflow.com/questions/37362554/minimize-the-number-of-curand-states-stored-during-a-mc-simulation/37381193#37381193) I haven’t read [the paper](https://arxiv.org/pdf/2301.03598.pdf) you indicated. ---
**Author:** ![Shaquille](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@Shaquille](https://forums.developer.nvidia.com/u/Shaquille)\ **Post date:** [September 30, 2023, 3:35am UTC](https://forums.developer.nvidia.com/t/what-is-the-relationship-between-block-idx-and-sm-idx/267991/6 "2023-09-30T03:35:40Z")
thanks for your kindly explanation I applied the ptx in my applicatioin： `asm("mov.u32 %0, %smid;" : "=r"(ret) );`，and I diasm this ptx, the result like this: ```auto /*0040*/ S2R R7, SR_VIRTUALSMID ; /* 0x0000000000077919 */ /* 0x000e620000004300 */ /*0050*/ SHF.L.U32 R2, R5, 0x1, RZ ; /* 0x0000000105027819 */ /* 0x001fca00000006ff */ /*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fca00078e0003 */ /*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*0080*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */ ``` I noticed that “SR\_VIRTUALSMID”, so, I think it is only virtual smid, instead of physical smid, my guess is right?