What is the relationship between the three USB3 SS PHY and the mux signals usb3_TXx usb3_RXx

Excuse the formatting disaster. They need fixed width fonts and allow spaces on this site…

I am trying to understand the relationship between the three USB3 interfaces and the four sets of signals in the PIN MUX table.

I am currently working on a design that will transition from Xavier to Orin SOMs and I am trying to figure out the USB differences.

Pin MUX map:

                             Xavier                                  Orin

USB3_TX0 UPHY_RX6/TX6 - K16,K17,B16,B17 UPHY_RX0/TX0 - J22,J23,A23,A24
USB3_TX1 UPHY_RX4/TX4 - J18,J19,A18,A19 * UPHY_RX1/TX1 - C22,C23,G22,G23
USB3_TX2 UPHY_RX1/TX1 - C22,C23,G22,G23 UPHY_RX20/TX20 - K32,K33,C34,C35
USB3_TX3 UPHY_RX11/TX11 - D12,D13,H12,H13 UPHY_RX7/TX7 - D12,D13,H12,H13 *
* = Not Functional?

My planned port assignments:

J1 USB3_TX2 UPHY_RX1/TX1 - C22,C23,G22,G23 UPHY_RX1/TX1 - C22,C23,G22,G23 USB2_0

J2 USB3_TX3 UPHY_RX11/TX11 - D12,D13,H12,H13 UPHY_RX7/TX7 - D12,D13,H12,H13 USB2_3 *

J3 USB3_TX0 UPHY_RX6/TX6 - K16,K17,B16,B17 UPHY_RX20/TX20 - K32,K33,C34,C35 USB2_1 Conditional POP

J4 USB2_TX2

We are planning in running in Config #2 so USB 3.1(P0) is missing on the Orin solution.

  1. Do USB2 ports have to match USB3 ports? In other words – Can I use USB2_0 with USB3_3 on a connector?

  2. How do the 4 USB UPHY pin group connections relate to the 3 USB3 devices in the SOIC?

  3. Some documents show 4 USB3 XUSBA (Orin Series SoC Technical Reference V1.0 page 5583) while others show three. How is this resolved? Are there issues with the silicon that have one of the USBs not function? I notice USB 3.1 (P1) is missing on Xavier and USB 3.1 (P3) is missing on Orin.

  4. Will my planned port assignments work?

Thanks in advance,

Hi,
We are working on adaptation guide of Orin. There is a section about USB lane mapping. Will update once it is published.

I don’t think that my questions will be answered by an adaptation guide.

What I need are separate guides to how the USB interfaces are mapped in the Xavier and Orin. The guide should specifically clarify the answers to my questions, especially the question of why there are 4 ports in the pin map spreadsheet and Technical reference but only three ports claimed in the specifications and how the USB 2.0 and USB 3.x ports are related.

Also, could someone tell me if my port pin mapping will work.


               Xavier                                  Orin


J1 USB3_TX2   UPHY_RX1/TX1 -   C22,C23,G22,G23  UPHY_RX1/TX1 -   C22,C23,G22,G23  - USB2_0
J2 USB3_TX3   UPHY_RX11/TX11 - D12,D13,H12,H13  UPHY_RX7/TX7 -   D12,D13,H12,H13 
 - USB2_3 *
J3 USB3_TX0   UPHY_RX6/TX6 -   K16,K17,B16,B17  UPHY_RX20/TX20 - K32,K33,C34,C35 
 - 
USB2_1 Conditional POP   
J4 USB2_TX2

The answer is UPHY are different in Orin and Xavier.

We only support one kind of UPHY config in Xavier and 2 kinds of config for Orin. These two are not fully compatible.

You can check the document in the download center first.

USB2 ports are not part of UPHY, so they do not matter here. It could be configured in software. That is what adaptation guide will teach you.

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