What is the SYS_RESET* state before the POWER_EN active?

I am designing a custom carrier board for the Jetson Nano SoM and I’ve come across something that is worrying me.
As per the design guide, it is required that the power rails (1.8V and 3.3V) of the carrier board to not be active until the system has fully booted which is indicated by the de-assertation of the SYS_RESET* pin of the module.
As for my design, there is about 900ms delay between applying 5V to VDD_IN of the module and the enabling of POWER_EN. I know for sure that when POWER_EN becomes active, SYS_RESET* is asserted and than de-asserted after the system boots.
I am using the SYS_RESET* to enable the my 5v to 3V3 step down regulator.
My concern is the 900ms delay between VDD_IN available and POWER_EN active. What is the state of the SYS_RESET* at this point, isn’t it pulled up to VDD_1V8? If so, my power rails will be active before POWER_EN becomes active.

Note about my design:
1- I have included a weak pull down resistor to the SYS_RESET* pin:

2- The SYS_RESET* pin is directly tied to the EN pin of the 5v to 3v3 step-down converter

3- I noticed in someone else’s design that there is a 10K series resistor between SYS_RESET* and the EN pin of the converter, why is that?

Please refer to below power on sequence in Design Guide. SYS_RESET* is low and will be high only ~82ms after POWER_EN is high.

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