What reset signal is driven-low by the Jetson AGX ORIN Module, when user initiates a “reset” command in Uboot or Linux?

PERIPHERAL_RESET_N is an input only to the module
SYS_RESET_N is bidirectional but it is controlled by module’s internal power sequencer, not by software, so I really couldn’t figure out which signal it is driven at software reset, from either Figure 5-1 or Figure 5-6 in the Design Guide.
I couldn’t find any software reset related signal from Development Kits Schematics P3737 document.

It’s MODULE_SHDN_N.

But MODULE_SHDN_N is a power-down request, not a reset signal. How would Carrier card be able to differentiate if it is a reset request or a power shutdown reset? Esp. when multiple notes recommend to gate MODULE_SHDN_N with input MODULE_POWER_ON signal. Once MODULE_SHDN_N is asserted low, it will drag input MODULE_POWER_ON signal low, then shutdown the module power, based on the note on D.G V1.2 page 22.

How does software reset the module without shutdown module powers?

FYI, Design Guide MODULE_SHDN_N pin-definition: “Module Shutdown Request. Used to inform carrier board that a shutdown request has occurred on-module (either software shutdown via SoC, or thermal shutdown). A 10kΩ pull-up to 1.8V is present on the module.”

Hi, NV gents. Any updates on this?

We are checking internally, will update once available.

There is no explicit pin on Orin that indicates an internal SW reset has occurred. Internal SW reset does not propagate to the IO pin. One way to set an indicator is to use the internal watchdog timer and use WDT_RESET_OUTA (GP63) or WDT_RESET_OUTB (GP21) as the indicator. Both signals are available on the CVM connector.

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Glad to clarify there is no output pin, and thanks for the recommendation.

One quick question though:
Assuming we don’t use watchdog, that means the module watchdog will not be kicked on at all. In this case, when initiating a software reset, would either pin of WDT_RESET_OUTA (GP63) or WDT_RESET_OUTB (GP21) be asserted low when module goes through a software reset cycle?
Or did you recommend software to toggle the pin low before issuing a reset command?

As said, if don’t use watch dog, then “There is no explicit pin on Orin that indicates an internal SW reset has occurred. Internal SW reset does not propagate to the IO pin”.