We developed a platform using the T30. We have been having a yield hit on the production line of our boards for failing to communicate with our Ethernet controller over PCIe. We have traced it back to the Tegra3 and confirmed it is not a training issue because the PCIe clock/data never start. I’ve traced it back to the Register in the Public T_PCIE2_RP_VEND_XP Bit30. This is a read only register. From the TRM it states, “This read-only bit tells status of Data Link Layer in XP. This bit was added before the DL Link Active Reporting feature was introduced in the official PCI-Express Specification. It asserts when
the DL enters the InitFC2 phase of training. This means that DL_UP will assert before the
DL_LINK_ACTIVE bit asserts.”
Can anyone tell me what in the hardware sets this bit?