What's ADU pipeline?

Accelerated Computing CUDA CUDA Programming and Performance
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I read description in Kernel Profiling Guide :: Nsight Compute Documentation
Address Divergence Unit. The ADU is responsible for address divergence handling for branches/jumps. It also provides support for constant loads and block-level barrier instructions.
But when there is address divergence? All threads in a warp access different place in global memory?
Could anyone give me an example when address divergence handling is needed.

2

Greg gives a brief example of ADU activity here.

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