When integrating an Ethernet switch in Jetson Xavier, it does not work

안녕하세요 저는 jetson agx xavier industrial 모델에서 기존 이더넷파이(88e1512)에 RGMII 로 연결되어있고… mdc/mdio는 범퍼를 거쳐 이더넷 파이와 이더넷스위치(88e6390x) 모두 연결되어있습니다.

그리고 이더넷파이는 mdi로 스위치와 연결되어있습니다.

tegra194-platforms-eqos.dtsi
디바이스 트리를 수정중인데… 작동되지않습니다.
확인 부탁드립니다.

ethernet@2490000 {
	interrupts =	<0 194 0x4>,    /* common */
			<0 186 0x4>,    /* tx0 */
			<0 190 0x4>;    /* rx0 */
	/* rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
	 * 0x0 = Not enabled, 0x1 = Enabled for AV
	 * 0x2 = Enabled for Legacy, 0x3 = Reserved
	 */
	nvidia,rxq_enable_ctrl = <2>;
	nvidia,num-dma-chans = <1>;
	nvidia,dma-chans = <0>;
	nvidia,num-mtl-queues = <1>;
	nvidia,mtl-queues = <0>;
	nvidia,rx-queue-prio = <0x2>;
	nvidia,tx-queue-prio = <0x0>;
	/* 1=enable, 0=disable */
	nvidia,pause_frames = <1>;
	nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;
	phy-mode = "rgmii-id";
	phy-handle = <&phy>;
	nvidia,max-platform-mtu = <16383>;

	fixed-link {
    		speed = <1000>;
		full-duplex;
	};
	
	
	mdio {
		compatible = "nvidia,eqos-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		phy: phy@0 {
			reg = <0>;
			interrupt-parent = <&tegra_main_gpio>;
			interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
			marvell,copper-mode;
			/* Setup LED[2] as interrupt pin (active low) */
			marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
		};
		
		switch0: switch@0 {
		
			compatible = "marvell,mv88e6190";
			#address-cells = <1>;
			reg = <0>;
			dsa,member = <0 0>;
		
			///* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
		       nvidia,phy-iface-mode = <0>;
		       
		       //ethernet switch mode 1:10G 0:5G
		       nvidia,uphy-gbe-mode = <1>;
		       

			//reset-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				
				port@0 {
					reg = <0>;
					label = "lan1";
					//phy-handle = <&phy0>;
				};

				port@1 {
					reg = <1>;
					label = "lan2";
				};

				port@2 {
					reg = <2>;
					label = "lan3";
				};
				
				port@3 {
					reg = <3>;
					label = "lan4";
				};

				port@4 {
					reg = <4>;
					label = "lan5";
				};

				port@5 {
					reg = <5>;
					label = "lan6";
				};
				port@6 {
					reg = <6>;
					label = "lan7";
				};
				port@7 {
					reg = <7>;
					label = "lan8";
				};


		};
	};
};
	

};

Hi insu8897,

Are you using Xavier NX or AGX Xavier Industrial?
Devkit or custom board?
Whats’ your Jetpack version in use?

Please share the block diagram of your connection between Jetson module, Ethernetpi, Ethernet switch.

and the full dmesg for further check.

If this is for etherent switch, then only need that fixed link node. Phy node shall not be needed.

These properties are meaningless too. These are for Orin. Not Xavier.

/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
nvidia,phy-iface-mode = <0>;
//ethernet switch mode 1:10G 0:5G
nvidia,uphy-gbe-mode = <1>;

hello, @KevinFFF Thanks for your reply.

I’m using a custom AGX Xavier industrial board.
I downloaded the L4T Release 35.4.1 source, modified the device tree, built it, and flashed it.
Additionally, I will add a hardware block diagram of our board.

also @WayneWWW As advised, I modified the device tree and applied it. I will also attach the dmesg file.
However, when I removed the PHY node, it said that the PHY could not be found, so I couldn’t turn it up with the ifconfig command.
eth0 in dmesg is a USB Ethernet separate from the Ethernet Pi.

    ethernet@2490000 {
	interrupts =	<0 194 0x4>,    /* common */
			<0 186 0x4>,    /* tx0 */
			<0 190 0x4>;    /* rx0 */
	/* rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
	 * 0x0 = Not enabled, 0x1 = Enabled for AV
	 * 0x2 = Enabled for Legacy, 0x3 = Reserved
	 */
	nvidia,rxq_enable_ctrl = <2>;
	nvidia,num-dma-chans = <1>;
	nvidia,dma-chans = <0>;
	nvidia,num-mtl-queues = <1>;
	nvidia,mtl-queues = <0>;
	nvidia,rx-queue-prio = <0x2>;
	nvidia,tx-queue-prio = <0x0>;
	/* 1=enable, 0=disable */
	nvidia,pause_frames = <1>;
	nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;
	phy-mode = "rgmii-id";
	//phy-handle = <&phy>;
	nvidia,max-platform-mtu = <16383>;

	mdio {
		compatible = "nvidia,eqos-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		
		switch0: switch@0 {
			compatible = "marvell,mv88e6190";
			reg = <1>;
			interrupt-parent = <&tegra_main_gpio>;
			interrupts = <TEGRA194_MAIN_GPIO(A, 3) IRQ_TYPE_LEVEL_LOW>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				
			       switch0port0: port@0 {
	          			reg = <0>;
	           			label = "rgmii-id";
	            			phy-mode = "rgmii-id";
	            			fixed-link {
	               			 speed = <1000>;
	                			full-duplex;
	            			};
	       		 };
				port@1 {
	           			 reg = <1>;
	            			label = "lan1";
	        		};
	       		 
		         	port@2 {
	           			 reg = <2>;
	            			label = "lan2";
	        		};
	        		
		         	port@3 {
	           			 reg = <3>;
	            			label = "lan3";
	        		};
		         	port@4 {
	           			 reg = <4>;
	            			label = "lan4";
	        		};
		         	port@5 {
	           			 reg = <5>;
	            			label = "lan5";
	        		};
		         	port@6 {
	           			 reg = <6>;
	            			label = "lan6";
	        		};
		         	port@7 {
	           			 reg = <7>;
	            			label = "lan7";
	        		};
		         	port@8 {
	           			 reg = <8>;
	            			label = "lan8";
	        		};
		         	port@9 {
	           			 reg = <9>;
	            			label = "lan9";
	        		};

			};

		};
	};
};

dmesg_240625.txt (59.4 KB)

Have you ever validate your such design before? For Jetson, only below design listed in Design Guide is supported.

@Trumany Thank you for answer.

  1. Is there any way to use Ethernet in our hardware design?

  2. We need several Ethernet ports connected to the AGX Xavier industrial module.
    Like the jetson design guide you mentioned, would it be correct to remove the existing 88E1512 in the enet phy part and use an Ethernet switch that supports RGMII connection?

We have no other suggestion than that in the Design Guide. You may need to check with PHY/switch vendor for how to implement multi ports design. Regarding your current design, at least the 88E1512 MDIO is necessary connected to Xavier.

@Trumany The previously uploaded image was incorrect. I will correct it.
MDIO is also branched and connected to 88E1512.

Is it possible to control 2 mdio connections on jetson agx xavier?

We don’t have such experience can be shared. You should check with vendor for the design first.

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