When the device boot, GPIO30 has a level transition.like this.How should I modify so that GPIO30 is always low
When the GPIO30 level changes, the device boot information：
[17:36:42:547]
[17:36:42:734]
[17:36:42:734] <0xff><0xe2>␍␊
[17:36:42:734] [0000.095] W> RATCHET: MB1 binary ratchet value 4 is too large than ratchet level 2 from HW fuses.␍␊
[17:36:42:734] [0000.103] I> MB1 (prd-version: 1.5.1.0-t194-41334769-59d8a47d)␍␊
[17:36:42:734] [0000.109] I> Boot-mode: Coldboot␍␊
[17:36:42:734] [0000.112] I> Chip revision : A02P␍␊
[17:36:42:734] [0000.115] I> Bootrom patch version : 15 (correctly patched)␍␊
[17:36:42:734] [0000.120] I> ATE fuse revision : 0x200␍␊
[17:36:42:734] [0000.123] I> Ram repair fuse : 0x0␍␊
[17:36:42:734] [0000.127] I> Ram Code : 0x2␍␊
[17:36:42:734] [0000.129] I> rst_source : 0x0␍␊
[17:36:42:734] [0000.132] I> rst_level : 0x0␍␊
[17:36:42:734] [0000.135] I> Boot-device: eMMC␍␊
[17:36:42:774] [0000.138] W> DEVICE_PROD: device prod is not initialized.␍␊
[17:36:42:774] [0000.143] W> DEVICE_PROD: device prod is not initialized.␍␊
[17:36:42:774] [0000.160] I> sdmmc DDR50 mode␍␊
[17:36:42:805] [0000.164] W> DEVICE_PROD: device prod is not initialized.␍␊
[17:36:42:805] [0000.169] W> No valid slot number is found in scratch register␍␊
[17:36:42:805] [0000.175] W> Return default slot: _a␍␊
[17:36:42:805] [0000.178] I> Active Boot chain : 0␍␊
[17:36:42:805] [0000.181] I> Boot-device: eMMC␍␊
[17:36:42:805] [0000.185] E> MB1_PLATFORM_CONFIG: device prod data is empty in MB1 BCT.␍␊
[17:36:42:805] [0000.191] E> MB1_PLATFORM_CONFIG: Failed to initialize device prod.␍␊
[17:36:42:805] [0000.199] I> Temperature = 30500␍␊
[17:36:42:805] [0000.202] W> Skipping boost for clk: BPMP_CPU_NIC␍␊
[17:36:42:805] [0000.206] W> Skipping boost for clk: BPMP_APB␍␊
[17:36:42:855] [0000.210] W> Skipping boost for clk: AXI_CBB␍␊
[17:36:42:855] [0000.214] W> Skipping boost for clk: AON_CPU_NIC␍␊
[17:36:42:855] [0000.218] W> Skipping boost for clk: CAN1␍␊
[17:36:42:855] [0000.222] W> Skipping boost for clk: CAN2␍␊
[17:36:42:855] [0000.226] I> Boot-device: eMMC␍␊
[17:36:42:855] [0000.229] I> Boot-device: eMMC␍␊
[17:36:42:855] [0000.238] I> Sdmmc: HS400 mode enabled␍␊
[17:36:42:855] [0000.243] I> ECC region[0]: Start:0x0, End:0x0␍␊
[17:36:42:855] [0000.247] I> ECC region[1]: Start:0x0, End:0x0␍␊
[17:36:42:855] [0000.251] I> ECC region[2]: Start:0x0, End:0x0␍␊
[17:36:42:855] [0000.255] I> ECC region[3]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.259] I> ECC region[4]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.264] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000␍␊
[17:36:42:898] [0000.269] I> Non-ECC region[1]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.274] I> Non-ECC region[2]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.278] I> Non-ECC region[3]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.283] I> Non-ECC region[4]: Start:0x0, End:0x0␍␊
[17:36:42:898] [0000.288] W> MB1_PLATFORM_CONFIG: Rail ID 9 not found in pmic rail config table.␍␊
[17:36:42:898] [0000.295] E> FAILED: Thermal config␍␊
[17:36:42:898] [0000.298] W> DEVICE_PROD: device prod is not initialized.␍␊
[17:36:42:928] [0000.307] W> MB1_PLATFORM_CONFIG: Rail ID 7 not found in pmic rail config table.␍␊
[17:36:42:928] [0000.314] E> FAILED: MEMIO rail config␍␊
[17:36:42:928] [0000.330] I> scrub mode: full dram␍␊
[17:36:42:961] [0000.334] E> FUSE: Failed to verify ECID.␍␊
[17:36:42:961] [0000.337] I> Boot-device: eMMC␍␊
[17:36:42:961] [0000.347] I> sdmmc bdev is already initialized␍␊
[17:36:43:006] [0000.384] W> No fuse-bypass data␍␊
[17:36:43:006] [0000.391] W> MB1_PLATFORM_CONFIG: Rail ID 8 not found in pmic rail config table.␍␊
[17:36:43:069] [0000.424] I> MB1 done␍␊
[17:36:43:069] ␍␊
[17:36:43:069]
[17:36:43:069] <0xff><0xfd><0xff><0xe0>main enter␍␊
[17:36:43:069] SPE VERSION #: R01.00.14 Created: Sep 19 2018 @ 11:03:21␍␊
[17:36:43:069] HW Function test␍␊
[17:36:43:069] Start Scheduler.␍␊
[17:36:43:069] in late init␍␊
[17:36:43:069] <0xff><0xe2>␊
[17:36:43:069] [0000.433] I> Welcome to MB2(TBoot-BPMP) (version: 00.00.2018.32-mobile-28aef4f2)␍␊
[17:36:43:069] [0000.433] I> DMA Heap @ [0x526fa000 - 0x52ffa000]␍␊
[17:36:43:069] [0000.434] I> Default Heap @ [0xd486400 - 0xd48a400]␍␊
[17:36:43:069] [0000.435] E> DEVICE_PROD: Invalid value data = 70020000, size = 0.␍␊
[17:36:43:069] [0000.440] W> device prod register failed␍␊
[17:36:43:069] [0000.444] I> Boot-device: eMMC␍␊
[17:36:43:069] [0000.447] I> Boot_device: SDMMC_BOOT instance: 3␍␊
[17:36:43:123] [0000.453] I> sdmmc-3 params source = boot args␍␊
[17:36:43:123] [0000.456] I> sdmmc bdev is already initialized␍␊
[17:36:43:123] [0000.460] I> sdmmc-3 params source = boot args␍␊
[17:36:43:123] [0000.466] I> Found 15 partitions in SDMMC_BOOT (instance 3)␍␊
[17:36:43:123] [0000.473] I> Found 37 partitions in SDMMC_USER (instance 3)␍␊
[17:36:43:123] [0000.476] W> No valid slot number is found in scratch register␍␊
[17:36:43:123] [0000.481] W> Return default slot: _a␍␊
[17:36:43:123] [0000.484] I> Active Boot chain : 0␍␊
[17:36:43:123] [0000.488] I> parsin
hello 417383384,
do you have pinmux spreadsheet customization to update the board configuration?
please check developer guide, Pinmux and GPIO Configuration for reference,
thanks
hello 417383384,
you had to update the pin configuration using a pinmux spreadsheet for the appropriate platform, and then flash the new configuration to the developer kit.
so, had you also convert the .dtsi file generated by Excel spreadsheets into a .cfg file with pinmux-dts2cfg.py? you should perform image flashing to update the cfg file.
thanks
I have done this，update .cfg file and flash.
hello 417383384,
may I know this level transition happened during which bootloader stage? MB1, MB2, CBoot?
you may also refer to Jetson AGX Xavier Series Boot Flow, thanks
According to the device boot information, it happened before cboot.I am not sure if it is in MB1 or MB2
Hello 417383384,
In your .cfg file, can you make this change:
under ##Pinmux for used pins##
remove pinmux.0x02430050 = 0x00000058; // pull-up
and add pinmux.0x02430050 = 0x00000054; // pull-down
Let us know the results.
hello shgarg,
I modified the GPIO30 configuration to output low level in Excel spreadsheets, and generated the cfg file.
in the cfg file:
under ##Pinmux for used pins##
pinmux.0x02430050 = 0x00000000; # soc_gpio20_pq0: rsvd0, tristate-disable, input-disable, lpdr-disable.
When the device boot, GPIO30 has a level transition.and output low.
when I modify pinmux.0x02430050 to 0x00000058 or 0x00000054,and update image.
When the device boot, GPIO30 is always high level.
Hello 417383384,
Can you also try following and let me know if this is also going in level transition.
In .cfg file:
##Pinmux for gpio-input pins##
Remove:
pinmux.0x02212c00 = 0x00000001; # CONFIG Q0
pinmux.0x02430050 = 0x00000000; # GPIO soc_gpio20_pq0
##Pinmux for gpio-output-low pins##
Add:
pinmux.0x02212c00 = 0x00000003; # CONFIG P0
pinmux.0x02212c0c = 0x00000000; # CONTROL P0
pinmux.0x02212c10 = 0x00000000; # OUTPUT P0
pinmux.0x0243d008 = 0x00000000; # GPIO soc_gpio20_pq0
##Pinmux for used pins##
pinmux.0x02430050 = 0x00000000; # soc_gpio20_pq0: rsvd0, tristate-disable, input-disable, lpdr-disable
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