Where are I can find the jetson TX1 send the IIC data to MIPI sensor?

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

Where are I can find the jetson TX1 send the IIC data to MIPI sensor? I use R28.2

2

hello sensor_test,

you’re asking function calls that send commands through i2c, right?

  1. there’s kernel failure if you meet the i2c communication failure.
    for example,
tegra-i2c 3180000.i2c: no acknowledge from address 0x10
  1. please refer to our reference camera drivers.
static int imx185_write_reg(...)
3

Where are define the send iic data to sensor at device file if I will capture a picture?

4

For example, I send the below command ,
what iic function or command will triggle at device file?

v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=50
5

hello sensor_test,

in generally, we control camera sensor device through i2c.
may I have more details about which specific function you’re looking for ?

moreover,
I would suggest you check the code flow start from VI driver, there are several v4l2 I/O controls being trigger when you access the camera sensor, thanks

sources/kernel/kernel-4.4/drivers/media/platform/tegra/camera/vi/channel.c
6

Now I use the imx219 sensor.
I add a imx219 dtsi file.now can find the "/dev/video0"device.

Does the imx219.c and imx219_mode_tbls.h file MUST need modify？

now i find the error,

tegra_channel_error_status:error 20022 frame 6618
7

hello sensor_test,

this looks like the same issue you’re asking here: https://devtalk.nvidia.com/default/topic/1033195
let’s tracking at the same discussion thread.
thanks

8

I use logic analyzer the find the TX1 can imx219_mode_tbls.h file init table data below.
but now I can not find the sensor output picture some data.

static struct reg_8 mode_3280x2464[] = {
	{IMX219_TABLE_WAIT_MS, 10},
	/* software reset */
	{0x0103, 0x01},
	/* global settings */
	{0x30EB, 0x05},
	{0x30EB, 0x0C},
	{0x300A, 0xFF},
	{0x300B, 0xFF},
	{0x30EB, 0x05},
	{0x30EB, 0x09},
	{0x0114, 0x01},
	{0x0128, 0x00},
	{0x012A, 0x0C},
	{0x012B, 0x00},
	{0x0160, 0x09},
	{0x0161, 0xC3},
	{0x0162, 0x0D},
	{0x0163, 0x78},
	{0x0164, 0x00},
	{0x0165, 0x00},
	{0x0166, 0x0C},
	{0x0167, 0xCF},
	{0x0168, 0x00},
	{0x0169, 0x00},
	{0x016A, 0x09},
	{0x016B, 0x9F},
	{0x016C, 0x0C},
	{0x016D, 0xD0},
	{0x016E, 0x09},
	{0x016F, 0xA0},
	{0x0170, 0x01},
	{0x0171, 0x01},
	{0x0174, 0x00},
	{0x0175, 0x00},
	{0x018C, 0x0A},
	{0x018D, 0x0A},
	{0x0301, 0x05},
	{0x0303, 0x01},
	{0x0304, 0x02},
	{0x0305, 0x02},
	{0x0306, 0x00},
	{0x0307, 0x4C},
	{0x0309, 0x0A},
	{0x030B, 0x01},
	{0x030C, 0x00},
	{0x030D, 0x98},
	{0x4767, 0x0F},
	{0x4750, 0x14},
	{0x47B4, 0x14},
	/* stream on */
	{0x0100, 0x01},
9

this looks like the same issue you’re asking here: https://devtalk.nvidia.com/default/topic/1033195
please move your update there and tracking at the same discussion thread.