Where can I get old jetson nano image built at 2018?

some one give me a code which define tegra_asoc_audio_clock_info for outof tree module build,

struct tegra_asoc_audio_clock_info {
struct device *dev;
struct snd_soc_card *card;
enum tegra_asoc_utils_soc soc;
struct clk *clk_pll_base;
struct clk *clk_pll_out;
struct clk *clk_aud_mclk;
struct clk *clk_ahub;

but in the kernel the same structure use different one. (which delete the clk_ahub)
struct tegra_asoc_audio_clock_info {
struct device *dev;
struct snd_soc_card *card;
enum tegra_asoc_utils_soc soc;
struct clk *clk_pll_base;
struct clk *clk_pll_out;
struct clk *clk_aud_mclk;
----------struct clk *clk_ahub;

I also find the dtb doesn’t use clk_ahub
please tell me which jetson nano version don’t need clk_ahub ?

Hello!

You can see a list of all the L4T releases here:

The first release that supported Jetson Nano was made in 2019 and so there were no releases that supported Jetson Nano in 2018. It is really not clear what you are intending to do, but it is recommended that you use the latest release rather than an older release and make the necessary changes.

Regards,
Jon

Hi Jonathanh:

It is good idea to move to latest one, but some one left old code which only work on old version like 32.3.1.

So I had to find the image for that version.

I will check the link that you provided. Someone told me that it is tough to get contact with nvida FAE.

Looks it is not true.

Thanks very much

Please keep in touch.

Zhigang Jin

Hello Zhigang,

If the code is based upon r32.3.1, then it should not be too difficult to get it working with the latest. However, r32.3.1 is available here if you should need it …

https://developer.nvidia.com/l4t-3231-archive

Jon

Hi Jonathanh:

I get the image based on your instruction.

Another question , we connect a pcie switch on the pcie0, and want to make the rest pcie0_rst to come later 100 ms after pcio_clock appear.

Do you have some advice to how to change code to make rst signal come later ?

Thanks

Zhigang

Thank you.

image002.jpg

Hello!

I focus in audio related issues/questions. I will ask if we can pull in someone to help with the above question.

Jon

Hi Jonathanh:

It is great news that know you are focus on audio.

Actually , I have another mission to bring up a audio codec which connect to jetsonnaon p40 pin, it is sgtl5000,

I want to try use fe-pi-audio-z-v2 card at first, but I don’t know what device tree is good , and what file should I need build.

If you have any instruction for fe-pi-audio-z-v2, please share with me.

Regards

Zhigang jin

Hello Zhigang Jin,

This audio module is supported in L4T. To configure the Jetson Nano to use this module please see the following info …

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fhw_setup_jetson_io.html%23

Please note that if you are using r32.3.1, there are a couple workarounds required for the ‘jetson-io’ tool to work and these are documented in the above document.

Regards,
Jon

Please apply below patch

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 63c0e343d388..893412efa35a 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2004,7 +2004,7 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
                afi_writel(port->pcie, value, ctrl);
        }
 
-       usleep_range(1000, 2000);
+       msleep(100);
 
        /* deAssert PEX_RST_A */
        if (gpio_is_valid(port->rst_gpio)) {

Hi Vidyas:

I am build the image as you said, and will give you update today.

Thanks for you quick response.

Zhigang

Hi vidyas:

We add a pcie switch at pcie 0, and want to put a ssd on that switch, but jetson nano cpu doesn’t see the ssd.

Do I need change device tree or tegra_pci.c so that system can detect a device is connected to the pcie switch?

Zhigang

Are you implying that Tegra is able to see the PCIe switch but not the SSD connected behind the PCIe switch? If yes, then, I don’t see any issue from Tegra side and you may have to debug either at PCIe switch level or SSD?
BTW, have you tried connecting the SSD directly to the Tegra and see if it gets enumerated by the system?

Hi Vidyas:

Add this delay still can’t make the rts come later than clock. But make the rts more early.

Attach two file is oscilloscope capture

1 pcierfclk-before.jpg :no any delay

  1. pcie_rclk_afert.jpg :add 100 ms as your code

It looks the delay drive the rst to wrong direction.

Should I call `tegra_pcie_port_reset in some other location, instead of current place?```

``

`The lspci -vv give a log lspci_log.txt,and I can’t find my ssd device from pci switch.```

`Do you find some error from lspci log?```

``

`Regards```

Zhigang

PCIe_RFCLK-before.JPG

PCIe_RCLK-after.JPG

lspci_log.txt (5.39 KB)

I do see REFCLK with lower magnitude appearing before PERST de-assertion. Isn’t that REFCLK at all? Although I’m not sure why is its magnitude less in the beginning through.
If possible, can you increase the time to a higher value (say 1000ms for example) and see if REFCLK continues to be like this (i.e. with lower magnitude) or would it ever go up?

Hi :

I am reading the jetson nano dts file and can’t understand the syntax of following line.

What is the meaning of the red line “ ids = “>=3448-0000-100”, “>=3448-0002-100”; “?

I want to know whether my overlay part is executed because of this line.

Regards

Zhigang

fragement@0 {

ids = “>=3448-0000-100”, “>=3448-0002-100”;

override@0 {

target = <0xad>;

overlay {

channel@0 {

ti,rail-name = “POM_5V_IN”;

};

channel@1 {

ti,rail-name = “POM_5V_GPU”;

};

};

device tree overlays get applied during the bootloader stage and by the time kernel starts booting, final DT (after all overlays applied according to their conditions) would be available to the kernel

What is the meaning of the line “ ids = “>=3448-0000-100”, “>=3448-0002-100”; “?
i can’t find any doc about this line

These are board revisions. In some scenarios, we may have to make few DT changes specific to certain board revisions. If you are not using custom base/IO boards, then, you don’t have to worry about these.

Hi zhigang,

Have you managed to get issue resolved?
Any result can be shared?

Hi:

Yes , we have progress to enable audio feature on dev kit.

Now, we are working on real product board, and will give you update after production board working also.

Thank you

Zhigang