Where is DP LT driver code

I want to check the DP driver source code to find out below DP display log. But can’t find where the DP driver code is. Can anyone help me ?

[ 1.543158] tegradc 15200000.nvdisplay: disp0 connected to head0->/host1x/sor1
[ 1.543191] generic_infoframe_type: 0x87
[ 1.543289] tegradc 15200000.nvdisplay: DT parsed successfully
[ 1.543341] tegradc 15200000.nvdisplay: Display dc.ffffff800bd50000 registered with id=0
[ 1.548065] tegra_nvdisp_bandwidth_register_max_config: max config iso bw = 15681600 KB/s
[ 1.548072] tegra_nvdisp_bandwidth_register_max_config: max config EMC floor = 933000000 Hz
[ 1.548078] tegra_nvdisp_bandwidth_register_max_config: max config hubclk = 300000000 Hz
[ 1.548322] tegradc 15200000.nvdisplay: vblank syncpt # 8 for dc 0
[ 1.548332] tegradc 15200000.nvdisplay: vpulse3 syncpt # 9 for dc 0
[ 1.551658] tegradc 15200000.nvdisplay: hdmi: invalid prod list prod_list_hdmi_board
[ 1.551667] tegradc 15200000.nvdisplay: hdmi: tegra_hdmi_tmds_range_read(bd) failed
[ 1.557530] tegradc 15210000.nvdisplay: disp1 connected to head1->/host1x/sor
[ 1.557574] tegradc 15210000.nvdisplay: parse_dp_settings: No dp-lt-settings node
[ 1.557684] tegradc 15210000.nvdisplay: DT parsed successfully
[ 1.557725] tegradc 15210000.nvdisplay: Display dc.ffffff800bed0000 registered with id=1
[ 1.558010] tegradc 15210000.nvdisplay: vblank syncpt # 11 for dc 1
[ 1.558028] tegradc 15210000.nvdisplay: vpulse3 syncpt # 12 for dc 1
[ 1.558873] tegradc 15210000.nvdisplay: Bootloader disp_param detected. Detected mode: 640x480 (on 0x0mm) pclk=50347983
[ 1.563128] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 1.565429] tegradc 15210000.nvdisplay: probed
[ 1.920627] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 1.920632] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 1.920637] dp lt: state 0 (Reset), pending_lt_evt 0
[ 1.920647] dp lt: link training force disable
[ 1.920651] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 1.969984] tegradc 15210000.nvdisplay: dc_poll_register 0x41: timeout
[ 1.969989] tegradc 15210000.nvdisplay: dc timeout waiting for DC to stop
[ 2.061740] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 2.061745] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 2.061750] dp lt: state 0 (Reset), pending_lt_evt 0
[ 2.062799] max77620-power max20024-power: Event recorder REG_NVERC : 0x54
[ 2.063464] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 2.063472] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 2.063997] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 2.064011] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 2.064020] dp lt: tx_pu: 0x20
[ 2.064958] dp lt: CR done
[ 2.064963] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 2.064969] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 2.067111] dp lt: CE done
[ 2.067117] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)

Find “dp.c” in your kernel source.

If you don’t have kernel source, you can download it over the l4t-archive website.

I have the kernel source code.

I can find one dp.c in kernel source as below.

kernel_4.9.253_r32.6.1/kernel/kernel-4.9$ find . -name “dp.c”
./drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

But I did not see the logs in this file.

Kernel sources directory is not only kernel-4.9.

ok. Find the code under nvidia/drivers/video/tegra/dc
Thanks a lots, @WayneWWW

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