In NVIDIA Jetson TX2,
According to the TX2 Technical Reference Manual(refer to Chapter-2.3), Parker has only 320KB of actual SysRAM, and the base address is 0x0_3000_0000.
According to the ATF code, the size of TZDRAM is 4MB (refer to ‘arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h’), and the base address is equal to the base address of SysRAM (‘refer to arm-trusted-firmware/plat/nvidia/tegra/ soc/t186/platform_t186.mk’).
In other words, TZDRAM must be in SysRAM.
But this does not match the TX2 reference manual, so where is TZDRAM?
TZRAM is on-chip RAM which act like a normal RAM by default; ATF doesn’t use TZRAM.
TZ-DRAM is majority for ARM trusted application (TA) code to access security data/code under DRAM.
the start address of TZ-DRAM is configured in the makefile; there is an assumption that maximum allowed size for TZ-DRAM is 32MB.
the size and alignment are configured by BCT, (i.e. tegra186-mb1-bct-misc-si.cfg), you may also check
I clearly know that TZ-DRAM should be in DRAM, but the makefile configures the starting address of TZ-DRAM to be 0x3000_0000 and the starting address of DRAM to 0x8000_0000, which is very confusing.
In addition, I found tegra186-mb1-bct-misc-si-l4t.cfg and tegra186-mb1-bct-misc-si-l4t-storm.cfg, but they did not describe sw_carveout.tzdram_carveout_size.
Now, I start to wonder if my board is T186. How can I determine whether the development board is 186 or 194?
it’s TX2 if you’re working with t186; t194 was the chip version for Xavier.
you may also looking for kernel messages about its chip version, for example,
$ dmesg | grep DTS
Yes, I can confirm this now, it is TX2.
Now it is TZ-DRAM that makes me very confused, please help me.