Which I/Os are available to the Cortex-R5 cores?

I understand that the upcoming Jetpack release will include some support for developing for one/some of the built-in Cortex-R5 cores.
Given that there are a large number of those cores in the Xavier, which of those are we able to target?
And which external I/Os are available for those cores?

Hi snarky,

You can refer to AGX Xaver TRM chapter: Always-On Cluster (AON) and SPE, which may answer your questions.


I read about the Always-On Cluster, but it doesn’t tell me which signals are routed where.
The Excel spreadsheet also doesn’t seem to have choices for the AOC to the I/O output signals.
Maybe I missed something, or maybe this will become apparent with the upcoming release?