Which party should I modify for MIPI 4 lanes on the DTB file?

Autonomous Machines Jetson & Embedded Systems Jetson Nano
1

Hello,

I am trying to import new CMOS sensor to Jetson Nano board. So, I made a new DTB files and driver files following your “Sensor Software Driver Programming Guide (Welcome — Jetson Linux<br/>Developer Guide 34.1 documentation)”
So far, I can communicate with the CMOS sensor through I2C, and modify any registers.
However, I can not see any images with my V4l2 Application(I works well with IMX219(Raspberry pi camera)).
I think I missed some parts with DTB parameters.
Can you give me some tips about DTB parameters for MIPI 4 lanes CMOS.

  • more information -
  1. It is connected to CSI4 4 lanes located on Jetson Nano Developments board bottom side.
  • is it right tegra_sinterface is “serial_f” for CSI4??
  1. I got this message “video4linux video0: frame start syncpt timeout!0” during V4L2 application is running.

Thanks

3

Enable the debug print of the csi2_fops.c to check the status

4

Thank you for your tip.
First of all, I found a solution of first question.
If want to modify CSI port, then modify DTB file of “port-index” of CAM to value what you want.

I have another question.
The debug print of the csi2_fops.c is enabled and I got the following error message.
what does it mean of “EGRA_CSI_CILX_STATUS 0x0004004”

[ 310.529185] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 310.529191] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 310.529195] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 310.529199] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041

5

Have a check the TRM for the detail information.
The REG CSI_CSI_CILA_STATUS_0 tell the TEGRA_CSI_CILX_STATUS, looks like may be HW error suggest have scope to probe the all of the data line signal.