Why check VI register ,all return 0xBADF5100 ??

dear all,

I still need to ask a question about VI register!!

Why I check VI register (0x0x15c14034,0x15c14038,0x15c1403c) through devmem tools,

all return 0xBADF5100 ?????

It’s a little abnormal

Hi, please list the registers name, thanks.

dear Trumany,

  I check VI register (0x0x15c14034,0x15c14038,0x15c1403c),all return 0xBADF5100

registers name:
0x15c14034 – VI_CFG_INTERRUPT_STATUS_0 (important)

     0x15c14038     --  VI_CFG_INTERRUPT_MASK_0

     0x15c1403c     --  VI_CFG_PWM_CONTROL_0

The check method is as follows:
1. v4l2-ctl --set-fmt-video=width=1920,height=1080,pixelformat=BG10 --stream-mmap=1 --stream-count=10000 --stream-to=/tmp/stream.raw -d /dev/video0 &
2.busybox devmem 0x15c14034

Is there something wrong with my check method?

Looks like the base address not correct.
They should be like below.

0x15f0503c: VI_CFG_PWM_CONTROL_0
0x15f05038: VI_CFG_INTERRUPT_MASK_0
0x15f05034: VI_CFG_INTERRUPT_STATUS_0

dear ShaneCCC,

Is this the address of VI0?


How to calculate base address of VI0/1/2/3/4/5/6   ?

thanks very much

I’m not sure how to calculate VI base address after check SOC datasheet

dear ShaneCCC

Does VI not distinguish between base address ?

I check VI0 and VI2 and found that they were both the same base address

hello JiaZW,

please check Sensor Driver Programming Guide for the [Port Index] session which shows the port index mapping diagram.
you might also refer to the register table below for more details.

$TOP/kernel_src/kernel/nvidia/drivers/media/platform/tegra/vi/vi_irq.c

dear JerryChang,

I check VI register, found that the register(Horizontal down-scaling 1 0x15f0b018) already had data.

Does this mean that VI has received the data??

hello JiaZW,

there’s an alternative way to check VI works properly besides dumping the register.

  1. access the sensor with v4l2 standard control.
$ v4l2-ctl -d /dev/video0 --set-fmt-video=width=2592,height=1944,pixelformat=RG10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100
  1. launch with gstreamer to preview the frame.
$ gst-launch-1.0 nvarguscamerasrc sensor-id=0 ! 'video/x-raw(memory:NVMM),width=1920, height=1080, framerate=30/1, format=NV12' ! nvoverlaysink -ev

please also check Camera Software Development Solution to have more details about applications to validate your sensor driver.
thanks

dear JerryChang,

Now, I failed to get video data through v4l2-ctl tools, report the following error:

“[ 3529.138194] tegra194-vi5 15c10000.vi: no reply from camera processor
[ 3529.138353] tegra194-vi5 15c10000.vi: vi capture dequeue status failed
[ 3529.138575] tegra194-vi5 15c10000.vi: channel error, resetting the channel”

I want to check the VI register to find out what the problem is .

@JiaZw
Enable the vi trace log to get more information.

https://elinux.org/Jetson_TX2/28.1_Camera_BringUp

hi ShaneCCC,

Can you please verify these are based on TRM? I am not sure how those are calculated. Can you have a brief explaination how register address and offset are put together? Thanks

0x15f0403c: VI_CFG_PWM_CONTROL_0
0x15f04038: VI_CFG_INTERRUPT_MASK_0
0x15f04034: VI_CFG_INTERRUPT_STATUS_0

is it 0x15f05 or 0x15f04 (where 0x4xxx is byte offset)

The TRM current release have problem for VI REG. Will update the TRM.