Why Jetson 35.2.1 reduced drive strength on CAM_I2C lines, which caused camera to fail?

Hi,
My camera worked, more or less, with Jetson 35.1.0 on Orin, but with Jetson 35.2.1 it is inaccessible via I2C.
I found that the following 2 registers:
PADCTL_G3_CFG2TMC_CAM_I2C_SDA_0 and PADCTL_G3_CFG2TMC_CAM_I2C_SCL_0 with 2 fields: CFG_CAL_DRVUP and CFG_CAL_DRVDN
used to have full drive strength in 35.1.0:
sudo busybox devmem 0x02430014
0x0001F000
sudo busybox devmem 0x0243001c
0x0001F000
But with 35.2.1 drive strength was reduced:
sudo ./busybox devmem 0x02430014
0x00003000
sudo ./busybox devmem 0x0243001c
0x00003000
And I2C cannot work anymore.
If I change these registers back
sudo busybox devmem 0x02430014 w 0x0001F000
sudo busybox devmem 0x0243001c w 0x0001F000
then camera is accessible again.

Question is why it was changed and in which configuration file.
The only file I know, which affects pinmux, is Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
does not contain the drive strength and did not change:
cam_i2c_scl_pp2 {
nvidia,pins = “cam_i2c_scl_pp2”;
nvidia,function = “i2c3”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
So, it must be somewhere else?
Thank you

hello jhnlmn,

there’s overlay changes check-in to r35.2.1,
could you please check you’ve overlay-name = "Jetson 24pin CSI Connector"; applied?

I guess not.
How to tell?
I installed twice : using SDK Manager and from command line using
sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1
the same was as I did with 35.1.0
and result is the same.
What should I do in order to apply this overlay?

hello jhnlmn,

you should running Jetson-IO utility to apply device tree overlay.
please see-also developer guide, Configuring the Jetson Expansion Headers.

I tried running
sudo /opt/nvidia/jetson-io/jetson-io.py
I tried all options for “Configure Jetson AGX CSI Connector” including various cameras and “Configure header pins manually”, but nothing works - nothing changes drive strength for I2C pins 75&77 - it always remains
sudo busybox devmem 0x02430014
0x00003000

Please,tell me exactly which DTS values to change.

hello jhnlmn,

this is device tree used by AGX Orin by default…/boot/dtb/kernel_tegra234-p3701-0000-p3737-0000.dtb

you may use the dtc utility to disassembler the dtb file into text file
for example, $ dtc -I dtb -O dts -o temp.dts tegra234.dtb
and, running below to convert the DTS into a new DTB file, $ dtc -I dts -O dtb -o output.dtb temp.dts

Of course, I am using dtc all the time, but I cannot find any hints how to configure these registers:
PADCTL_G3_CFG2TMC_CAM_I2C_SDA_0 and PADCTL_G3_CFG2TMC_CAM_I2C_SCL_0
I cannot find any differences in DTS file between Jetson 35.1.0 and 35.2.1 to explain why
these registers were reduced from 0x0001F000 to 0x00003000
I see in
https://docs.nvidia.com/jetson/archives/r35.2.1/DeveloperGuide/text/SD/Bootloader/PinmuxGpioConfig.html
settings like
pinmux_default: common {
nvidia,pins = “dap1_sclk_ps0”;
nvidia,function = “i2s1”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
but where are the setting for drive strength?

1 Like

hello jhnlmn,

please download Orin TRM for reference,
you may see-also [4.1 G3 PAD Control Registers] and you’ll also aware below footnote.

NOTE:
The G3 PAD Control Registers are collectively called PADCTL_A0 in the System Address Map.

let’s taking CAM_I2C_SDA as an example,
the address of PADCTL_G3_CFG2TMC_CAM_I2C_SDA_0 is… 0x02430000 + 0x14.

you may also open the cfg file to view the pin configurations.
as you can see, in the $OUT/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-prod-p3701-0000.dts
addr-mask-data = <0x02430014 0x0001f000 0x00003000>,
1st column is the address of PADCTL_G3_CFG2TMC_CAM_I2C_SDA_0.
2nd column is the bits to be mask, 0x1f000 it means bits 12:16 mask for setting CFG_CAL_DRVDN. you may also dig into TRM for register description.
3rd column is the value to be put in in the selected bit fields.

so, if you want to update the value in this field,
please modify the third parameter and re-flashing the board for confirmation.
thanks

Thank you, this works

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