With JetPack3.1, AON GPIOs (PAA03-06) can no longer be configured with io-high-voltage

The following pinmux configuration, generated using the pinmux spreadsheet, to set GPIO pins with 3V3 tolerance, worked in JetPack3.0 but no longer in 3.1.

can_gpio3_paa3 {
                                nvidia,pins = "can_gpio3_paa3";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                        };

                        // HUB_RESETn (3V3)
                        can_gpio4_paa4 {
                                nvidia,pins = "can_gpio4_paa4";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                        };

                        can_gpio5_paa5 {
                                nvidia,pins = "can_gpio5_paa5";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                        };

                        can_gpio6_paa6 {
                                nvidia,pins = "can_gpio6_paa6";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                        };

The kernel throws the error message like this.

[    0.707437] tegra186-pinctrl 2430000.pinmux: Config param 0007 (nvidia,io-high-voltage) not supported on group can_gpio5_paa5
[    0.719287] tegra186-pinctrl 2430000.pinmux: pin_config_group_set op failed for group 29
[    0.727761] tegra186-pinctrl 2430000.pinmux: Error applying setting, reverse things back
[    0.736263] tegra186-pinctrl 2430000.pinmux: failed to select default state

The TX2 datasheet shows IO voltage of these pins are 3V3 capable, is this a JetPack3.1 specific bug?

GPIO3_PAA.03 C19 CAN1_ERR CAN #1 Error Input CMOS – 3.3V CZ
GPIO3_PAA.04 C20 CAN_WAKE CAN Wake Input CMOS – 3.3V CZ
GPIO3_PAA.05 E18 CAN0_ERR CAN #0 Error Input CMOS – 3.3V CZ
GPIO3_PAA.06 C17 CAN1_STBY CAN #1 Standby Output CMOS – 3.3V CZ

@rong1129
Could you try “nvidia,io-hv” instead of "“nvidia,io-high-voltage”

@rong1129
Could you please share your dts file and dtb files?

The related section of my DTS file is shown above in Post #1. BTW, are you sure changing it to “nvidia,io-hv” would work? As if you look at the code in drivers/pinctrl/pinctrl-tegra.c below, it is either intentionally or mistakenly defined to something else (TEGRA_PINCONF_PARAM_RCV_SEL).

119 static const struct cfg_param {
 120         const char *property;
 121         enum tegra_pinconf_param param;
 122 } cfg_params[] = {
 123         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
 124         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 125         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 126         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 127         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 128         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 129         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
 130         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
 131         {"nvidia,io-high-voltage",      TEGRA_PINCONF_PARAM_E_IO_HV},
 132         {"nvidia,loopback",             TEGRA_PINCONF_PARAM_E_IO_HV},

@rong1129

I can’t tell it working or not, however TEGRA_PINCONF_PARAM_RCV_SEL set the same bit
Could you attached your dtb file.

s32 rcv_sel_bit:6;
        s32 e_io_hv_bit:6;

According to the TRM, page 912, bit 6 defines receiver path, whereas bit 5 is enabling IO high voltage:

Field Bit Position

E_IO_HV 5
E_INPUT 6

This pin seems didn’t define E_IO_HV, could you confirm the r27.1 set this reg correct by read the 0x0c303050 by the devmem2.

CAN GPIO3 does not support the IO_HV configurations. You can refer the TRM for this.

In customer pinmux spreadsheet, there is no option to enable/disable the 3.3V tolerance enable.

It seems you added “ENABLE” in this column (AT) and that’s why generated DTSI have the option for
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;

Please clear this cells in spreadsheet and then re-generate the DTSI.

Driver is improved to not support the filed to configure which is not supported by HW/IP.

Once you clear the cell, you will not see io-high-voltage option for this pin.

Page 49 of the TX2 SoM Datasheet (latest version, 1.1) indicates that the CAN pins are “CMOS - 3.3V”. Is this incorrect?

YES, the pins of CAN are 3.3V IO