Xavier AGX CHY can not work

xubin4952 · July 23, 2024, 2:57am

Hi Nvidia team，
When I config dts to cphy mode，I find cphy can not work，I can still receive dphy data.
Where I can see the code to confirm this problem?

this is my configuration

  		ar0231_a@50 {
  			compatible = "sony,imx390";
  			reg = <0x50>;
  			devnode = "video0";
  			physical_w = "3.674";
  			physical_h = "2.738";
  			sensor_model = "ar0231";
  			avdd-reg = "vana";
  			iovdd-reg = "vif";
  			delayed_gain = "true";
  			clocks = <0x04 0x24 0x04 0x24>;
  			clock-names = "extperiph1\0pllp_grtba";
  			mclk = "extperiph1";
  			reset-gpios = <0x0b 0x3e 0x00>;
  			vana-supply = <0x34>;
  			vif-supply = <0x35>;

  			mode0 {
  				mclk_khz = "24000";
  				num_lanes = [34 00];
  				tegra_sinterface = "serial_a";
  				vc_id = [30 00];
  				phy_mode = "CPHY";
  				discontinuous_clk = "yes";
  				dpcm_enable = "false";
  				cil_settletime = [30 00];
  				active_w = "3840";
  				active_h = "2160";
  				mode_type = "yuv";
  				pixel_phase = "uyvy";
  				csi_pixel_bit_depth = [38 00];
  				dynamic_pixel_bit_depth = [38 00];
  				readout_orientation = [30 00];
  				line_length = "3840";
  				inherent_gain = [31 00];
  				mclk_multiplier = "20.736";
  				pix_clk_hz = "497664000";
  				serdes_pix_clk_hz = "700000000";
  				gain_factor = "1000000";
  				min_gain_val = "1000000";
  				max_gain_val = "48000000";
  				step_gain_val = [31 00];
  				default_gain = "1000000";
  				min_hdr_ratio = [31 00];
  				max_hdr_ratio = [31 00];
  				framerate_factor = [31 00];
  				min_framerate = [36 00];
  				max_framerate = "30";
  				step_framerate = [31 00];
  				default_framerate = "30";
  				exposure_factor = "1000000";
  				min_exp_time = "110";
  				max_exp_time = "166577";
  				step_exp_time = [31 00];
  				default_exp_time = "16657";
  				embedded_metadata_height = [30 00];
  			};

  			ports {
  				#address-cells = <0x01>;
  				#size-cells = <0x00>;

  				port@0 {
  					reg = <0x00>;

  					endpoint {
  						vc-id = <0x00>;
  						port-index = <0x00>;
  						bus-width = <0x01>;
  						remote-endpoint = <0x36>;
  						phandle = <0x288>;
  					};
  				};
  			};
  		};

Does this mean we must set chpy mode work in 3 lane

image985×713 37.1 KB

JerryChang · July 23, 2024, 3:34am

hello xubin4952,

may I double confirm the L4T release version you’re working with,
you may examine the release tag, $ cat /etc/nv_tegra_release for confirmation.

besides, it looks like an old code, which has been revised in the latest release version.
please moving to the latest JP-5 release version, JetPack 5.1.3 (l4t-r35.5.0) if that’s feasible.

xubin4952 · August 1, 2024, 6:16am

Hi Jerry，
This is my version，it seems R35.50，so it is not a software version problem right？How can I debug this problem with code ?

$ cat /etc/nv_tegra_release
# R35 (release), REVISION: 5.0, GCID: 35550185, BOARD: t186ref, EABI: aarch64, DATE: Tue Feb 20 04:46:31 UTC 2024

JerryChang · August 1, 2024, 7:00am

hello xubin4952,

JP-5.1.3/r35.5.0 already changed to parse the PHY mode settings via device tree
for instance,

static int csi5_stream_set_config(..)
        ...
        u32 phy_mode = read_phy_mode_from_dt(chan);
        bool is_cphy = (phy_mode == CSI_PHY_MODE_CPHY);

please ensure you’re configured sensor to CPHY mode, and it’s outputting MIPI signaling correctly.
you may also follow below steps to enable VI tracing logs, which may gathering more details for reference.
for instance,

echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo > /sys/kernel/debug/tracing/trace
cat /sys/kernel/debug/tracing/trace

xubin4952 · August 1, 2024, 7:22am

Hi Jerry，
I can not find “read_phy_mode_from_dt” in function csi5_stream_set_config.
Below is the code.

static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
	u32 csi_port, int csi_lanes)
{
	struct tegra_csi_device *csi = chan->csi;
	struct tegra_channel *tegra_chan =
			v4l2_get_subdev_hostdata(&chan->subdev);

	struct camera_common_data *s_data = chan->s_data;
	const struct sensor_mode_properties *mode = NULL;

	unsigned int cil_settletime = 0;
	unsigned int lane_polarity = 0;
	unsigned int index = 0;
	int vi_port = 0;

	struct CAPTURE_CONTROL_MSG msg;
	struct nvcsi_brick_config brick_config;
	struct nvcsi_cil_config cil_config;
	bool is_cphy = (csi_lanes == 3);
	dev_dbg(csi->dev, "%s: stream_id=%u, csi_port=%u\n",
		__func__, stream_id, csi_port);

	/* Attempt to find the brick config from the device tree */
	if (s_data) {
		int idx = s_data->mode_prop_idx;

		dev_dbg(csi->dev, "cil_settingtime is pulled from device");
		if (idx < s_data->sensor_props.num_modes) {
			mode = &s_data->sensor_props.sensor_modes[idx];
			cil_settletime = mode->signal_properties.cil_settletime;
			lane_polarity = mode->signal_properties.lane_polarity;
		} else {
			dev_dbg(csi->dev, "mode not listed in DT, use default");
			cil_settletime = 0;
			lane_polarity = 0;
		}
	} else if (chan->of_node) {
		int err = 0;
		const char *str;

		dev_dbg(csi->dev,
			"cil_settletime is pulled from device of_node");
		err = of_property_read_string(chan->of_node, "cil_settletime",
			&str);
		if (!err) {
			err = kstrtou32(str, 10, &cil_settletime);
			if (err) {
				dev_dbg(csi->dev,
					"no cil_settletime in of_node");
				cil_settletime = 0;
			}
		}
		/* Reset string pointer for the next property */
		str = NULL;
		err = of_property_read_string(chan->of_node, "lane_polarity",
			&str);
		if (!err) {
			err = kstrtou32(str, 10, &lane_polarity);
			if (err) {
				dev_dbg(csi->dev,
					"no cil_settletime in of_node");
				lane_polarity = 0;
			}
		}
	}

	/* Brick config */
	memset(&brick_config, 0, sizeof(brick_config));
	brick_config.phy_mode = (!is_cphy) ?
		NVCSI_PHY_TYPE_DPHY : NVCSI_PHY_TYPE_CPHY;

	/* Lane polarity */
	if (!is_cphy) {
		for (index = 0; index < NVCSI_BRICK_NUM_LANES; index++)
			brick_config.lane_polarity[index] = (lane_polarity >> index) & (0x1);
	}

	/* CIL config */
	memset(&cil_config, 0, sizeof(cil_config));
	cil_config.num_lanes = csi_lanes;
	cil_config.lp_bypass_mode = is_cphy ? 0 : 1;
	cil_config.t_hs_settle = cil_settletime;

	if (s_data && !chan->pg_mode)
		cil_config.mipi_clock_rate = read_mipi_clk_from_dt(chan) / 1000;
	else
		cil_config.mipi_clock_rate = csi->clk_freq / 1000;

	/* Set NVCSI stream config */
	memset(&msg, 0, sizeof(msg));
	msg.header.msg_id = CAPTURE_CSI_STREAM_SET_CONFIG_REQ;

	msg.csi_stream_set_config_req.stream_id = stream_id;
	msg.csi_stream_set_config_req.csi_port = csi_port;
	msg.csi_stream_set_config_req.brick_config = brick_config;
	msg.csi_stream_set_config_req.cil_config = cil_config;

	if (tegra_chan->valid_ports > 1)
		vi_port = (stream_id > 0) ? 1 : 0;
	else
		vi_port = 0;

	return csi5_send_control_message(tegra_chan->tegra_vi_channel[vi_port], &msg,
							&msg.csi_stream_set_config_resp.result);
}

This is the log

# tracer: nop
#
# entries-in-buffer/entries-written: 47/47   #P:8
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/0:2-94      [000] ....   711.366904: rtcpu_vinotify_event: tstamp:22827290216 cch:0 vi:0 tag:CHANSEL_PXL_EOF channel:0x23 frame:36059 vi_tstamp:730460280480 data:0x0000000004370002
     kworker/0:2-94      [000] ....   711.366907: rtcpu_vinotify_event: tstamp:22827290373 cch:0 vi:0 tag:ATOMP_FRAME_DONE channel:0x23 frame:36059 vi_tstamp:730460281024 data:0x0000000000000000
     kworker/0:2-94      [000] ....   711.366908: rtcpu_vinotify_event: tstamp:22827290509 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36059 vi_tstamp:730460291680 data:0x00000000020201a7
     kworker/0:2-94      [000] ....   711.366909: rtcpu_vinotify_event: tstamp:22827290661 cch:0 vi:0 tag:FE channel:0x00 frame:36059 vi_tstamp:730460404768 data:0x0000000000000020
     kworker/0:2-94      [000] ....   711.366909: rtcpu_vinotify_event: tstamp:22827290800 cch:0 vi:0 tag:ATOMP_FE channel:0x00 frame:36059 vi_tstamp:730460404832 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366910: rtcpu_vinotify_event: tstamp:22827290950 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36059 vi_tstamp:730460424128 data:0x00000000000201a7
     kworker/0:2-94      [000] ....   711.366928: rtcpu_vinotify_event: tstamp:22827291084 cch:0 vi:0 tag:FS channel:0x00 frame:36060 vi_tstamp:730461728576 data:0x0000000000000010
     kworker/0:2-94      [000] ....   711.366928: rtcpu_vinotify_event: tstamp:22827291239 cch:0 vi:0 tag:ATOMP_FS channel:0x00 frame:36060 vi_tstamp:730461728608 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366929: rtcpu_vinotify_event: tstamp:22827291374 cch:0 vi:0 tag:CHANSEL_PXL_SOF channel:0x23 frame:36060 vi_tstamp:730461991360 data:0x0000000000000001
     kworker/0:2-94      [000] ....   711.366930: rtcpu_vinotify_event: tstamp:22827291523 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36060 vi_tstamp:730461997088 data:0x00000000080201a8
     kworker/0:2-94      [000] ....   711.366930: rtcpu_vinotify_event: tstamp:22827291662 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730462149408 data:0xcd9ce50010000000
     kworker/0:2-94      [000] ....   711.366931: rtcpu_vinotify_event: tstamp:22827291811 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730462174880 data:0x00000000310001a9
     kworker/0:2-94      [000] ....   711.366931: rtcpu_vinotify_event: tstamp:22827381717 cch:0 vi:0 tag:CHANSEL_PXL_EOF channel:0x23 frame:36060 vi_tstamp:730476139808 data:0x0000000004370002
     kworker/0:2-94      [000] ....   711.366932: rtcpu_vinotify_event: tstamp:22827381871 cch:0 vi:0 tag:ATOMP_FRAME_DONE channel:0x23 frame:36060 vi_tstamp:730476140352 data:0x0000000000000000
     kworker/0:2-94      [000] ....   711.366932: rtcpu_vinotify_event: tstamp:22827382006 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36060 vi_tstamp:730476151040 data:0x00000000020201a8
     kworker/0:2-94      [000] ....   711.366934: rtcpu_vinotify_event: tstamp:22827807606 cch:0 vi:0 tag:FE channel:0x00 frame:36060 vi_tstamp:730476264128 data:0x0000000000000020
     kworker/0:2-94      [000] ....   711.366935: rtcpu_vinotify_event: tstamp:22827807750 cch:0 vi:0 tag:ATOMP_FE channel:0x00 frame:36060 vi_tstamp:730476264192 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366935: rtcpu_vinotify_event: tstamp:22827807903 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36060 vi_tstamp:730476283456 data:0x00000000000201a8
     kworker/0:2-94      [000] ....   711.366951: rtcpu_vinotify_event: tstamp:22827808034 cch:0 vi:0 tag:FS channel:0x00 frame:36061 vi_tstamp:730477587904 data:0x0000000000000010
     kworker/0:2-94      [000] ....   711.366952: rtcpu_vinotify_event: tstamp:22827808188 cch:0 vi:0 tag:ATOMP_FS channel:0x00 frame:36061 vi_tstamp:730477587968 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366953: rtcpu_vinotify_event: tstamp:22827808323 cch:0 vi:0 tag:CHANSEL_PXL_SOF channel:0x23 frame:36061 vi_tstamp:730477850720 data:0x0000000000000001
     kworker/0:2-94      [000] ....   711.366953: rtcpu_vinotify_event: tstamp:22827808481 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36061 vi_tstamp:730477856416 data:0x00000000080201a9
     kworker/0:2-94      [000] ....   711.366954: rtcpu_vinotify_event: tstamp:22827808616 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730478007712 data:0xcd9ce20010000000
     kworker/0:2-94      [000] ....   711.366955: rtcpu_vinotify_event: tstamp:22827808765 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730478030720 data:0x00000000310001aa
     kworker/0:2-94      [000] ....   711.366956: rtcpu_vinotify_event: tstamp:22827923017 cch:0 vi:0 tag:CHANSEL_PXL_EOF channel:0x23 frame:36061 vi_tstamp:730491999168 data:0x0000000004370002
     kworker/0:2-94      [000] ....   711.366957: rtcpu_vinotify_event: tstamp:22827923173 cch:0 vi:0 tag:ATOMP_FRAME_DONE channel:0x23 frame:36061 vi_tstamp:730491999712 data:0x0000000000000000
     kworker/0:2-94      [000] ....   711.366957: rtcpu_vinotify_event: tstamp:22827923309 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36061 vi_tstamp:730492010368 data:0x00000000020201a9
     kworker/0:2-94      [000] ....   711.366958: rtcpu_vinotify_event: tstamp:22827923459 cch:0 vi:0 tag:FE channel:0x00 frame:36061 vi_tstamp:730492123488 data:0x0000000000000020
     kworker/0:2-94      [000] ....   711.366958: rtcpu_vinotify_event: tstamp:22827923599 cch:0 vi:0 tag:ATOMP_FE channel:0x00 frame:36061 vi_tstamp:730492123488 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366959: rtcpu_vinotify_event: tstamp:22827923759 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36061 vi_tstamp:730492142816 data:0x00000000000201a9
     kworker/0:2-94      [000] ....   711.366960: rtcpu_vinotify_event: tstamp:22827923890 cch:0 vi:0 tag:FS channel:0x00 frame:36062 vi_tstamp:730493447264 data:0x0000000000000010
     kworker/0:2-94      [000] ....   711.366961: rtcpu_vinotify_event: tstamp:22828324456 cch:0 vi:0 tag:ATOMP_FS channel:0x00 frame:36062 vi_tstamp:730493447296 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366961: rtcpu_vinotify_event: tstamp:22828324597 cch:0 vi:0 tag:CHANSEL_PXL_SOF channel:0x23 frame:36062 vi_tstamp:730493710048 data:0x0000000000000001
     kworker/0:2-94      [000] ....   711.366962: rtcpu_vinotify_event: tstamp:22828324751 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36062 vi_tstamp:730493715744 data:0x00000000080201aa
     kworker/0:2-94      [000] ....   711.366962: rtcpu_vinotify_event: tstamp:22828324884 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730493865472 data:0xcd9ce50010000000
     kworker/0:2-94      [000] ....   711.366963: rtcpu_vinotify_event: tstamp:22828325037 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730493890944 data:0x00000000310001ab
     kworker/0:2-94      [000] ....   711.366964: rtcpu_vinotify_event: tstamp:22828431112 cch:0 vi:0 tag:CHANSEL_PXL_EOF channel:0x23 frame:36062 vi_tstamp:730507858496 data:0x0000000004370002
     kworker/0:2-94      [000] ....   711.366965: rtcpu_vinotify_event: tstamp:22828431274 cch:0 vi:0 tag:ATOMP_FRAME_DONE channel:0x23 frame:36062 vi_tstamp:730507859040 data:0x0000000000000000
     kworker/0:2-94      [000] ....   711.366966: rtcpu_vinotify_event: tstamp:22828431411 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36062 vi_tstamp:730507869696 data:0x00000000020201aa
     kworker/0:2-94      [000] ....   711.366966: rtcpu_vinotify_event: tstamp:22828431564 cch:0 vi:0 tag:FE channel:0x00 frame:36062 vi_tstamp:730507982816 data:0x0000000000000020
     kworker/0:2-94      [000] ....   711.366967: rtcpu_vinotify_event: tstamp:22828431704 cch:0 vi:0 tag:ATOMP_FE channel:0x00 frame:36062 vi_tstamp:730507982848 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366967: rtcpu_vinotify_event: tstamp:22828431858 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36062 vi_tstamp:730508002144 data:0x00000000000201aa
     kworker/0:2-94      [000] ....   711.366968: rtcpu_vinotify_event: tstamp:22828431990 cch:0 vi:0 tag:FS channel:0x00 frame:36063 vi_tstamp:730509306592 data:0x0000000000000010
     kworker/0:2-94      [000] ....   711.366969: rtcpu_vinotify_event: tstamp:22828432146 cch:0 vi:0 tag:ATOMP_FS channel:0x00 frame:36063 vi_tstamp:730509306656 data:0x0000000800000000
     kworker/0:2-94      [000] ....   711.366969: rtcpu_vinotify_event: tstamp:22828432279 cch:0 vi:0 tag:CHANSEL_PXL_SOF channel:0x23 frame:36063 vi_tstamp:730509569376 data:0x0000000000000001
     kworker/0:2-94      [000] ....   711.366970: rtcpu_vinotify_event: tstamp:22828432431 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:36063 vi_tstamp:730509575104 data:0x00000000080201ab
     kworker/0:2-94      [000] ....   711.366970: rtcpu_vinotify_event: tstamp:22828432570 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:730509735648 data:0xcd9ce20010000000

xubin4952 · August 1, 2024, 7:33am

Hi Jerry ，
Another question what is the difference between“csi4_fops.c” and “csi5_fops.c”?

JerryChang · August 1, 2024, 8:10am

hello xubin4952,

first of all, this is definitely not kernel source of r35.5.0 release version.
please visit jetson-linux-r3550 page for downloading [Driver Package (BSP) Sources] package.

they’re used by different Jetson series.
for instance, it’s Jetson TX2 Module | NVIDIA Developer, which using CSI driver, csi4_fops.c
Jetson Xavier series and Jetson Orin series they’re sharing the same CSI driver, csi5_fops.c

BTW,
your tracing logs looks correct, what did you meant CPHY cannot work, is there any failure reported?

xubin4952 · August 1, 2024, 9:14am

Hi Jerry，
Thank you for your reply.

version problem

Why I use cat /etc/nv_tegra_release command it seems the version is R35.5.0.
I download the packet，I find the code is in “DRIVERS” not in “SOURCES”. Is that right?

work log problem

I config the soc in CPHY mode ,but mipi tx work in DPHY mode ,I do not change the mode in mipi tx.
When I do not change the version of source .I just change the i’s_cphy = true’, The soc can work in cphy mode,or I should do other change for cphy mode.

static int csi5_stream_set_config(..)
        ...
        bool is_cphy = true;

I change the mipi tx to cphy mode.And I get the error below.

   kworker/1:2-130     [001] ....   729.309099: rtcpu_nvcsi_intr: tstamp:23409114581 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
     kworker/1:2-130     [001] ....   729.309100: rtcpu_nvcsi_intr: tstamp:23409114933 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
     kworker/1:2-130     [001] ....   729.309100: rtcpu_nvcsi_intr: tstamp:23409115298 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
     kworker/1:2-130     [001] ....   729.309100: rtcpu_nvcsi_intr: tstamp:23409115652 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080

JerryChang · August 2, 2024, 1:43am

hello xubin4952,

(1) it’s the release tag /etc/nv_tegra_release about which version flashing onto your target.
you should download the public release sources, there’ll be kernel_src.tbz2 package for kernel sources.
please see-also developer guide, Kernel Customization.

(2) VI tracing logs show the error code 0x80, which meant LP sequence error has detected on data lane.
normally, LP sequence it should follow by LP11->LP01->LP00->LP11 sequence. it’s more like a hardware issue.
may I also confirm what’s the sensor you’re working with, or, is it a MIPI generator for simulation?

xubin4952 · August 2, 2024, 2:19am

Hi Jerry ，
I want to confirm I just change thei’s_cphy = true’ in function “csi5_stream_set_config” below.
Can this make the soc work in cphy mode,or I should do other change for cphy mode.

static int csi5_stream_set_config(..)
        ...
        bool is_cphy = true;

I am using Deserializer to generator the mipi cphy signal.
I am not familiar with CHPY.Does CPHY have LP11->LP01->LP00->LP11 like DPHY?

JerryChang · August 2, 2024, 2:33am

hello xubin4952,

it’s okay to simply hack the boolean variable as CPHY mode, however, let’s based-on the same kernel version to avoid potential issues.
CPHY also had low-power sequence, but it’s based-on 3-lane config.

xubin4952 · August 2, 2024, 2:38am

Hi Jerry,

Does this mean I must config the mipi tx to 3 trio mode?
Can I config the mipi tx in 1 trio mode to test the function？

xubin4952 · August 2, 2024, 5:53am

Hi Jerry，
Please help me to confirm the problem below. I want to debug this problem today. Thank you!

JerryChang · August 2, 2024, 5:59am

hello xubin4952,

it’s okay to use 1-trio mode for testing.

FYI,
The Design Guidance in our documentation for C-PHY is based on 2.5Gsps validation at the module level. The platform is designed to support higher C-PHY rates at 4.5 Gsps, but, for CSI it is susceptible to multiple factors: such as… trace length, temperature, wear of the components, and MIPI Speeds.

xubin4952 · August 2, 2024, 6:38am

Hi Jerry,

I change to 1 trio mode，I get a new error， what does this mean？ How can I find the error list?
And which file print this log?

I can use 1 trio .What does “CPHY also had low-power sequence, but it’s based-on 3-lane config.” mean.
3-lane config mean 1trio A B C right?

JerryChang · August 2, 2024, 7:16am

hello xubin4952,

it still shows LP sequence error has detected, 0x9 represent the errors on data-lane and also clock-lane.

xubin4952 · August 2, 2024, 11:22am

Hi Jerry，

It seems like a hardware problem .I will check the hardware.

What does this log mean?

JerryChang · August 5, 2024, 1:52am

hello xubin4952,

CHANSEL_NOMATCH=0x3c9 represent its data type is detected as YUV422 8-bit, which seems mismatch with your device tree settings to report no-match failure.
please see-also Topic 234303 about CHANSEL_NOMATCH messages.

it looks promising since there’re FS (Frame-Start) and FE (Frame-End) in your VI tracing logs.
you should resolve that no-match issue, so that channel select should detect CHANSEL_PXL_SOF and CHANSEL_PXL_EOF as a good frame packet.

xubin4952 · August 6, 2024, 2:36am

Hi Jerry,
Thank you for your reply.

What is this problem represent for?

JerryChang · August 6, 2024, 5:06am

hello xubin4952,

we ignore that messages usually, could you please share complete VI tracing logs for checking.

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