Hi, I have been going through the documentation for the SPE/Cortex-R5 on the Xavier, but haven’t found any information about how the R5 image is actually loaded into memory on a cold boot. Can anyone point me in the right direction?
I am also interested in knowing if it’s possible to access the location where the R5 binary is stored. This is in hopes that I can update the R5 image using a custom firmware update method. Any help is much appreciated, thanks!
SPE R5 firmware is loaded in MB1 stage. Refer to https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fbootflow_jetson_xavier.html.
SPE R5 is running in SPE TCM, so it’s not possible to access that space through CCPLEX.
Regarding customer firmware update, I’ve replied in another thread: Jetson AGX Xavier SPE/Cortex-R5 Firmware Update
please check it and let me know if you have any problem.