Dear support team,
Please point me to where I can find the following information for Xavier SoC:
- EMC programming guide as mentioned in <Xavier_TRM_DP09253002.pdf> Ver 1.1 on page Page 6057 of 8287
- EMC register offsets and/or equivalent register names for accessing the DRAM mode registers on Xavier
o On Parker e.g. there is one called EMC_MRS_0 at offset 0xh in ch 18.104.22.168 on page 1256 of <Parker_TRM_DP07821001p.pdf> Ver 1.0p
o These registers might have different names and offsets on Xavier, I just could not find them in TRM, please help
- Where to find the EMC register offsets inside SW for Xavier (e.g. cboot source code <c-boot-L4T.r31.1>)
o There are some register definitions inside <c-boot-L4T.r31.1\hwinc-t19x\41334769\nvboot_sdram_param_generated.h> but I can’t find them used
o Source code or binary of the BCT containing these EMC registers
In case this is confidential information please refer me to one of your field representatives, we can check on existing NDAs.
We are a Semiconductor company delivering DRAM and intend to use the purchased Jetson AGX Xavier development kit to corner test/fine tune DRAM in-system.
Thanks & Best Regards