Xavier NX boot issues with POWER_EN glitch

Hey!

Thanks for making amazing Xavier NX device!

We have been working on building a custom carrier board for Xavier NX. We are using custom Power Logic (not an MCU) to power up our board. Due to the architecture of this Power Logic Circuit, we have a glitch at the beginning of the power ramp as shown below:

Power_EN signal as 12V rises:

SYS_RESET signal as 12V rises:

Our power regulators for other power supply other than 12V and 5V are switched on with SYS_RESET signal going HIGH.

Problem:
Xavier NX device doesn’t boot up. It seems that it tries to send initial boot messages on UART and then dies with gibberish UART. I’d suspect that this would happen when we have a glitch like that. However, we should be able to recover from that glitch. Do note that Jetson Nano boots perfectly fine with the same carrier board and same glitch in POWER_EN signal.

What would be helpful?
Please let us know if there are any other requirements for the Jetson Xavier NX to boot properly. For example, does Jetson Xavier NX need POWER_EN signal for at least 100ms before we pull it low and come back up? Would that be an issue when we have a situation with brown-out?

Thanks in advance! Have great development!

Hi, you should measure VDD_5V_SYS and POWER_EN. POWER_EN should be high after VDD_5V_SYS is stable enough. Also note the VDD_3V3_SYS should be enabled after SYS_RESET going high.

you should measure VDD_5V_SYS and POWER_EN. POWER_EN should be high after VDD_5V_SYS is stable enough.

Unfortunately, I don’t have a oscilloscope shot for VDD_5V_SYS and POWER_EN compared. However, from the oscilloscope shots I have shown, VDD_5V_SYS comes up as 12V goes above 6V. The first pulse in POWER_EN that you see there comes 80ms after VDD_5V_SYS is stable and above 4.75V. That’s how we’ve designed our system.

Due to the designed system behavior, we see that glitch. However, throughout the whole sequence, VDD_5V_SYS is stable.

The boot process starts when we see the first pulse in POWER_EN, and is abrupted by POWER_EN going low. According to my understanding, we should start booting again after that. (Correct me if I’m wrong).

SYS_RESET goes HIGH in both cases as you can see from the oscilloscope shot - showing that the device should boot up properly. EDIT: Which is does not

Also note the VDD_3V3_SYS should be enabled after SYS_RESET going high.

Regulator controlling VDD_3V3_SYS is Enabled by SYS_RESET signal.

Can you try to change logic circuit to eliminate the “glitch” on POWER_EN? Also you can do cross check with devkit carrier board if possible to make sure module has no problem.

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The module doesn’t have any issues. I’m working on eliminating the glitch there.

Thanks for your input!

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