Hi, I’m working on our custom board using xavier nx on L4T 32.7.3, and we met a problem.
our device tree of display is set as below
sor {
status = "okay";
// /delete-property/ nvidia,hpd-gpio;
nvidia,active-panel = <&sor0_hdmi_display>;
hdmi-display {
status = "okay";
};
dp-display {
status = "disabled";
};
};
sor1 {
status = "okay";
// /delete-property/ nvidia,hpd-gpio;
nvidia,active-panel = <&sor1_hdmi_display>;
hdmi-display {
status = "okay";
};
dp-display {
status = "disabled";
};
};
We use two HDMI out and output image to FPGA. But only one can output sor0(152100000), and the dmesg show this information, our sor1(15200000) not working.
[ 14.430467] tegradc 15200000.nvdisplay: hdmi: scdc scrambling status is reset, trying to reconfigure.
[ 19.550386] tegradc 15200000.nvdisplay: hdmi: scdc scrambling status is reset, trying to reconfigure.
[ 24.670313] tegradc 15200000.nvdisplay: hdmi: scdc scrambling status is reset, trying to reconfigure.
[ 29.790297] tegradc 15200000.nvdisplay: hdmi: scdc scrambling status is reset, trying to reconfigure.
and I noticed this information so its our FPGA’s configuration is not adapted to jetson.
https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3275/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/display_configuration.html#wwpID0E0DI0HA
So I do as this doc, modified our device tree like this
&sor1_hdmi_display {
status = "okay";
nvidia,fbcon-default-mode {
vmode = <0x400000>;
flags = <0x3>;
nvidia,v-ref-to-sync = <0x1>;
nvidia,h-ref-to-sync = <0x1>;
vsync-len = <400>;
vback-porch = <420>;
vfront-porch = <400>;
hsync-len = <700>;
hback-porch = <1080>;
hfront-porch = <700>;
vactive = <1080>;
hactive = <1920>;
clock-frequency = <27027000>;
};
disp-default-out {
nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
nvidia,out-hotplug-state = <1>; // TEGRA_HPD_STATE_FORCE_ASSERT
};
};
These parameters are provided to us by the FPGA.
Two hdmi out can work but this sor1 output is not normal
other hdmi out is like this
and we get these err message
[ 1.810296] tegradc 15200000.nvdisplay: sor_poll_register 0x15: timeout
[ 1.810303] tegradc 15200000.nvdisplay: dc timeout waiting for OR MODE = SAFE
[ 1.862234] tegradc 15200000.nvdisplay: sor_poll_register 0x16: timeout
[ 1.862242] tegradc 15200000.nvdisplay: dc timeout waiting for HEAD MODE = SLEEP
[ 2.564168] extcon-disp-state external-connection:disp-state: cable 47 state 0
[ 2.614227] tegradc 15200000.nvdisplay: dc_poll_register 0x41: timeout
[ 2.614232] tegradc 15200000.nvdisplay: dc timeout waiting for DC to stop
[ 2.666215] tegradc 15200000.nvdisplay: dc_poll_register 0x41: timeout
[ 2.666219] tegradc 15200000.nvdisplay: dc timeout waiting for DC to stop