[Xavier Nx] Failing eDP Link Training on DP1


We’ve designed a carrier board for the Xavier Nx 16GB module.

We’ve run into issues with our eDP<> LVDS Display bring-up.

Here’s a high-level overview of the hardware design:

  • DP1 ports configured for eDP (Aux, Main link, HPD)
  • NXP’s PTN3460I is used to convert eDP to LVDS [2-lane eDP]
  • LVDS to LCD T-Con board

Here’s what we’ve confirmed:

  • Pinmux DTSI and Device Tree are updated to reflect hardware modifications
  • I2C bus between Xavier Nx and PTN3460I is functioning as expected
  • eDP Aux comms is working [able to read custom EDID]

Where we start having issues:

  • The eDP main Link Training fails at the initial Clock Recovery step
  • I attached a log to show what we’re seeing failed_dp_cs_kernel.log (68.0 KB)

Open questions:

  1. Are there any known issues with integrating the NXP PTN3460 into the Jetson ecosystem?
  2. Are there any additional clock configurations required to properly mux the eDP clock on DP1’s ports?
  3. Any advice on how to narrow down why we are seeing issues with Link Training’s Clock Recovery?


please also test with jp4 first. We have no experience with PTN3460, but as I know, jp5 display driver is not as stable as jp4.

@WayneWWW Noted. We’ll downgrade the JetPack to see how it performs.

Can you elaborate on why you suspect the JetPack5 display driver isn’t as stable as JetPack4?

Because I already knew there are some known issues in jp5 driver…

@WayneWWW Does Nvidia have an errata that details the known issues with Jetpack 5, in particular with the display drivers?

You can test with jp4 first. I just want to avoid you took every issue altogether.

We can discuss about jp5 issue later…

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