Xavier PCIE EP bar configuration

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Bar4 is for atu_dma registers and bar0 is for dma buffer in xavier pcie ep mode. I can only find inbound_atu function in pcie-tegra-dw-ep.c, but it is used for inbound setting and not for bar setting.

  1. Where is bar0 and bar4 mapping setting?
  2. How can i bind bar2 with user-defined memory?
    thanks~
2

Hi,
for your first question, those are fixed in hardware hence you may not find any specific programming.
for your second question, endpoint mode driver already takes care of mapping system memory to BAR-2. I think this can be exposed to userspace through mmap. Although this is not readily available in the code, I think this can be tried out at your end and I don’t see any reason why it won’t work.

3

hi, vidyas, are there steps to set bar2? thanks

4

Yes

5

hi vidyas. Where can i find the steps to set up bar2? thanks

6

I find that there is no bar mask register for bar2, but bar0 and bar4 have mask register．So I can not set bar2 size. I use function inbound_atu to set bar2 mapping, but I can not read the correct data in RC. How can I configure bar2? thanks

7

Hi,

BAR2 is used for MSI-X vector table. Only BAR0 can be configured for our use cases.

Manikanta

8

thanks