Xavier pcie share memory access from user space

There are two xavier modules on our self-developed backplane. They are connected through a pcie. I have modified the kernel code with reference to the following link.

The endpoint and root port seem to work normally at present. On the end point side, I have obtained the initial physical address of the pcie. I can read and write pcie data through the busybox devmem command. When the offset address is less than 4M, the data on both sides can be synchronized, but when it exceeds 4M, the data on both sides are inconsistent, I don’t know How to call the remap_pfn_range() function in the pci-epf-nv-test.c file,Can you give me some sample code? We want to transmit data correctly within the 512M address range on both sides of the end point and root port.

we use jp4.4.1

A common case would be
a) accessing this memory through CPU using CPU-VA which we get from dma_alloc_coherent
b) accessing this memory through the device using IOVA which again we get from dma_alloc_coherent()

How should I access shared memory in user space through CPU-VA or IOVA?

Pls refer to

kernel/nvidia/drivers/pci/endpoint/functions/pci-epf-nv-test.c 
kernel/nvidia/drivers/misc/tegra-pcie-ep-mem.c

for reference.

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