Zero copy mem access patterns

Accelerated Computing CUDA CUDA Programming and Performance
1

Tim, are there any strict rules on the way mapped host memory should be accessed from the device ?
It is not clear from the SDK example provided …

2

What kind of rules do you expect? Don’t go out of bounds, don’t expect it to work cleanly if you are reading from one location and writing from another (CPU and GPU, GPU and other GPU, whatever)…

As far as performance goes, I think optimal access patterns will look a lot like GT200 coalescing.

3

May one thread access a bunch of data items without performance penalty ?

Something like this:

void Kernel(float* d_pMappedMemory)

{

	for (int i = 0; i < N; i++)

		fVar += d_pMappedMemory[base + thread.idx + i);

}

Under performance penalty I understand effects similar to ‘uncoalesced access’ issues.