Zynq PCIe endpoint and IGX

Autonomous Machines IGX Orin Support Forum IGX Developer Kit
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1

Hi all,

I have a custom board based on a Xilix Zynq Ultrascale+ SoC configured as PCIe endpoint (PS-PCIe Gen2x4) and I have to communicate with an Orin IGX (on PCIe slot 0).
The custom board boots regularly when PCIe 12V is stable but on IGX side the O.S. doesn’t enumerate the endpoint, on Zynq side I can see the boot process stuck on “wait for PCIe link up” status.
Rescan of PCI in the IGX has no effect.
If I program the Zynq after the IGX boot (blanking its flash memory) and after a PCI rescan then lspci shows the endpoint but a reboot command will freeze the IGX.
I also mounted the custom board on a PC and in this case the endpoint is enumerated by BIOS only when I force PCIe to “Gen2” instead of “auto” (in the BIOS) but after this setup all works fine, in my experience some chipset needs this setup with Xilinx PCIe.

Has anyone ever managed to connect an IGX with a PS-PCIe of a Zynq ?
Any suggestion about how to investigate this issue will be very appreciated :)
Tnx
Gianmarco

4

Hi gfiabane,

Is there any serial console log could be shared?

For IGX, please try to add max-link-speed = <2> to the PCIe controller in device tree.

5

Hi KevinFFF,

thanks for your reply.
On the IGX side I’m quite new, which of the many logs do you refer?
I have a doubt about max-link-speed, do this option reduce all the pcie nodes performance ? Can I specify this option for only PCIe slot 0 in device tree?

6

Are you using the IGX devkit?

Have you tried to connect the PIN3/PIN4/PIN11 of 12-pins header to capture serial console log?

No, it wouldn’t.
Yes, you can just configure that in the PCIe controller you are using for your Zynq device.

7

Hi KevinFFF,

unfortunately the max-link-speed doesn’t solve the problem.
The only way I found to enumarate my custom board is boot up IGX then program the SoC on the board and finally rescan pcie from Ubuntu.
Regarding the serial console, witch 12-pin header do you refer to?
Here: Connector Definitions - NVIDIA Docs there is only one 12-pin (J43 TPM Header ) in wich PIN11 is not connected, did you mean PIN6? Or one of the UARTs on J16/J33/J35 ?

8

Are you using custom carrier board for IGX?

For serial console…
Do you have J65 on your board?
Or could you access BMC console now? Serial console could also be accessed through BMC console with port 2200.

9

Is this still an issue to support? Any result can be shared?

10

Hi Kevin, I’m still investigating. I found a workaround but it isn’t a “clean boot” solution.

Gianmarco

11

May I know what your workaround is and what do you mean about “not a clean boot”?

12

Hi KevinFFF,

on Zynq side the System have to restart itself (a complete reboot) if linkup doesn’t occur after a timeout, then it can configure its bridge and wait for a first interaction with O.S. running on Tegra (a simple check on a flag set by HOST in EP DDR) and only at this point the Zynq can complete BAR configuration. Any other combination produces UEFI or Kernel to stuck and\or Zynq driver to go in exception condition.

1 Like
13

It seems you were testing with IGX SW 1.0DP before.
Have you updated to the latest IGX SW 1.0 Production release to verify?