# \#architecture-and-design **URL:** https://forums.developer.nvidia.com/tag/architecture-and-design/531.md [Latest](https://forums.developer.nvidia.com/latest.md) · [Categories](https://forums.developer.nvidia.com/categories.md) · [Tags](https://forums.developer.nvidia.com/tags.md) --- ## [FinC2E — Governance-First AI for AML/KYC & Audit-Ready Decision Support (Human-in-the-Loop)](https://forums.developer.nvidia.com/t/finc2e-governance-first-ai-for-aml-kyc-audit-ready-decision-support-human-in-the-loop/355159)
**Author:** [@bpm\_red\_academy](https://forums.developer.nvidia.com/u/bpm_red_academy)\ **Replies:** 3\ **Last updated:** [August 4, 2026, 11:00am UTC](https://forums.developer.nvidia.com/t/finc2e-governance-first-ai-for-aml-kyc-audit-ready-decision-support-human-in-the-loop/355159 "2026-08-04T11:00:30Z")
Hello NVIDIA Developer Community, I’m sharing FinC2E, a governance-first AI system designed for AML / KYC / CDD triage, risk classification, and audit-ready reasoning, built explicitly as an advisory layer — not an auton… --- ## [From Governance Runtime Assurance to Human-Directed Intelligence](https://forums.developer.nvidia.com/t/from-governance-runtime-assurance-to-human-directed-intelligence/373803)
**Author:** [@bpm\_red\_academy](https://forums.developer.nvidia.com/u/bpm_red_academy)\ **Replies:** 7\ **Last updated:** [June 19, 2026, 2:12pm UTC](https://forums.developer.nvidia.com/t/from-governance-runtime-assurance-to-human-directed-intelligence/373803 "2026-06-19T14:12:19Z")
From Governance Runtime Assurance to Human-Directed IntelligenceWorking note from BPM RED Academy / HumAI MightHub development In my previous posts, I explored the progression from deterministic inference toward governan… --- ## [From Deterministic Inference to Governance Runtime Assurance — Version 2 Control-Plane Architecture](https://forums.developer.nvidia.com/t/from-deterministic-inference-to-governance-runtime-assurance-version-2-control-plane-architecture/372011)
**Author:** [@bpm\_red\_academy](https://forums.developer.nvidia.com/u/bpm_red_academy)\ **Replies:** 0\ **Last updated:** [June 2, 2026, 12:27pm UTC](https://forums.developer.nvidia.com/t/from-deterministic-inference-to-governance-runtime-assurance-version-2-control-plane-architecture/372011 "2026-06-02T12:27:01Z")
From Deterministic Inference to Governance Runtime Assurance — Version 2 Control-Plane Architecture In earlier BPM RED Academy / HumAI MightHub development notes, I described a deterministic inference pipeline for regul… --- ## [Governance Runtime Assurance — Measuring Route Reliability Beyond Raw Inference Speed](https://forums.developer.nvidia.com/t/governance-runtime-assurance-measuring-route-reliability-beyond-raw-inference-speed/371626)
**Author:** [@bpm\_red\_academy](https://forums.developer.nvidia.com/u/bpm_red_academy)\ **Replies:** 0\ **Last updated:** [May 28, 2026, 6:08pm UTC](https://forums.developer.nvidia.com/t/governance-runtime-assurance-measuring-route-reliability-beyond-raw-inference-speed/371626 "2026-05-28T18:08:57Z")
Governance Runtime Assurance — Measuring Route Reliability Beyond Raw Inference Speed In the previous HumAI MightHub development cycle, I described the transition from single model execution toward Live Orchestration Int… --- ## [Live Orchestration Intelligence — Persistent Route Memory for Governance-Native AI Factory Control Planes](https://forums.developer.nvidia.com/t/live-orchestration-intelligence-persistent-route-memory-for-governance-native-ai-factory-control-planes/370812)
**Author:** [@bpm\_red\_academy](https://forums.developer.nvidia.com/u/bpm_red_academy)\ **Replies:** 0\ **Last updated:** [May 20, 2026, 12:27pm UTC](https://forums.developer.nvidia.com/t/live-orchestration-intelligence-persistent-route-memory-for-governance-native-ai-factory-control-planes/370812 "2026-05-20T12:27:46Z")
Live Orchestration Intelligence — Persistent Route Memory for Governance-Native AI Factory Control Planes In the previous development cycle, I described the transition from single model execution toward Mission Control … --- ## [Aggregate ECC Error Counter Clear Behavior Discrepancy Between RTX PRO 6000 Blackwell Server Edition and H100 PCIe](https://forums.developer.nvidia.com/t/aggregate-ecc-error-counter-clear-behavior-discrepancy-between-rtx-pro-6000-blackwell-server-edition-and-h100-pcie/364855)
**Author:** [@yjlee8](https://forums.developer.nvidia.com/u/yjlee8)\ **Replies:** 7\ **Last updated:** [April 14, 2026, 11:58pm UTC](https://forums.developer.nvidia.com/t/aggregate-ecc-error-counter-clear-behavior-discrepancy-between-rtx-pro-6000-blackwell-server-edition-and-h100-pcie/364855 "2026-04-14T23:58:39Z")
Hello, I would like to report a behavioral discrepancy in nvidia-smi -p 1 (Aggregate ECC error counter clear) between two GPU models, along with a contradiction found in official NVIDIA documentation. The full nvidia-sm… --- ## [E2E Sample scenario logs](https://forums.developer.nvidia.com/t/e2e-sample-scenario-logs/336499)
**Author:** [@anubhav.aggarwal](https://forums.developer.nvidia.com/u/anubhav.aggarwal)\ **Replies:** 1\ **Last updated:** [July 2, 2025, 11:06am UTC](https://forums.developer.nvidia.com/t/e2e-sample-scenario-logs/336499 "2025-07-02T11:06:22Z")
Hi Team, I’m trying to build an understanding of the Aerial cuBB architecture, and I’m facing some issues bring the system up. While I try to bring the system up, could I possibly get some E2E logs of a sample scenario… --- ## [Cache # and Slice # significance in an Xid 48 Message (Hopper)](https://forums.developer.nvidia.com/t/cache-and-slice-significance-in-an-xid-48-message-hopper/329679)
**Author:** [@goroz](https://forums.developer.nvidia.com/u/goroz)\ **Replies:** 0\ **Last updated:** [April 8, 2025, 8:39pm UTC](https://forums.developer.nvidia.com/t/cache-and-slice-significance-in-an-xid-48-message-hopper/329679 "2025-04-08T20:39:35Z")
I have logs of this nature found in journalctl. NVRM: Xid (PCI:0000:48:00): 48, pid=‘’, name=, An uncorrectable double bit error (DBE) has been detected on GPU in the L2 cache at cache 6, slice 1. I’ve been trying to m… --- ## [vGPU Configuration Architecture with KVM on Ubuntu](https://forums.developer.nvidia.com/t/vgpu-configuration-architecture-with-kvm-on-ubuntu/326521)
**Author:** [@kjh7976](https://forums.developer.nvidia.com/u/kjh7976)\ **Replies:** 0\ **Last updated:** [March 10, 2025, 5:06am UTC](https://forums.developer.nvidia.com/t/vgpu-configuration-architecture-with-kvm-on-ubuntu/326521 "2025-03-10T05:06:49Z")
This is my understanding of the vGPU architecture for Ubuntu KVM, am I wrong? --- ## [Is there Page Migration Engine in GPU architectures other than Pascal?](https://forums.developer.nvidia.com/t/is-there-page-migration-engine-in-gpu-architectures-other-than-pascal/315781)
**Author:** [@linxzhan9](https://forums.developer.nvidia.com/u/linxzhan9)\ **Replies:** 0\ **Last updated:** [December 5, 2024, 2:39am UTC](https://forums.developer.nvidia.com/t/is-there-page-migration-engine-in-gpu-architectures-other-than-pascal/315781 "2024-12-05T02:39:43Z")
Hello! It is clear that Page Migration Engine is first introduced in the Pascal architecture. However, there is not much information about whether it is presented in the subsequent generations of architectures like Turin… --- ## [Does SM have more FP units than those "cuda cores"?](https://forums.developer.nvidia.com/t/does-sm-have-more-fp-units-than-those-cuda-cores/290967)
**Author:** [@BskyBlue](https://forums.developer.nvidia.com/u/BskyBlue)\ **Replies:** 2\ **Last updated:** [April 27, 2024, 10:18am UTC](https://forums.developer.nvidia.com/t/does-sm-have-more-fp-units-than-those-cuda-cores/290967 "2024-04-27T10:18:23Z")
Have a compute-intensive cuda kernel that only do 32-bit FP fmad instructions RTX3070 TI → 48 SM → 128 CUDA cores / SM → Total of 6144 CUDA cores Interestingly, the result shows that each SM seems to have more FP… --- ## [Off-chip memory access](https://forums.developer.nvidia.com/t/off-chip-memory-access/282948)
**Author:** [@hnts03](https://forums.developer.nvidia.com/u/hnts03)\ **Replies:** 5\ **Last updated:** [February 16, 2024, 4:58pm UTC](https://forums.developer.nvidia.com/t/off-chip-memory-access/282948 "2024-02-16T16:58:30Z")
hello. I have a few questions about memory access to the GPU’s off-chip memory. when programming using CUDA, I can use the “memcpy” function to copy data to the CPU or GPU. To do this, I need to use the PCIe control… --- ## [AGX Xavier card MIPI-CSI Camera Communication](https://forums.developer.nvidia.com/t/agx-xavier-card-mipi-csi-camera-communication/276227)
**Author:** [@kaan\_zorluer](https://forums.developer.nvidia.com/u/kaan_zorluer)\ **Replies:** 2\ **Last updated:** [December 18, 2023, 8:45pm UTC](https://forums.developer.nvidia.com/t/agx-xavier-card-mipi-csi-camera-communication/276227 "2023-12-18T20:45:22Z")
We have connected another FPGA to the MIPI-CSI pins of the AGX Xavier board instead of the camera. That is, we are sending the camera data from another FPGA instead of the camera. But, the voltage level of the camera FPG… --- ## [GPU memory hierarchy](https://forums.developer.nvidia.com/t/gpu-memory-hierarchy/266468)
**Author:** [@1477957451](https://forums.developer.nvidia.com/u/1477957451)\ **Replies:** 0\ **Last updated:** [September 15, 2023, 2:35am UTC](https://forums.developer.nvidia.com/t/gpu-memory-hierarchy/266468 "2023-09-15T02:35:17Z")
How to categorize the on-chip memory and off-chip memory of the GPU. Is there any tutorial to learn it? --- ## [Query: Need information in respect of Nvidia Jetson: ORIN NX 8 GB](https://forums.developer.nvidia.com/t/query-need-information-in-respect-of-nvidia-jetson-orin-nx-8-gb/261646)
**Author:** [@varun.pratapsingh](https://forums.developer.nvidia.com/u/varun.pratapsingh)\ **Replies:** 4\ **Last updated:** [August 10, 2023, 10:26am UTC](https://forums.developer.nvidia.com/t/query-need-information-in-respect-of-nvidia-jetson-orin-nx-8-gb/261646 "2023-08-10T10:26:04Z")
Host processor to be used with your AI edge computing module Supported architecture (x86, ARM etc) Supported Host OS (Linux (which flavor of Linux), Windows) Supported hardware interface to Host (PCIe, USB etc) Do… --- ## [Xavier board with a Yocto OS and kubernetes on top / best practicies?](https://forums.developer.nvidia.com/t/xavier-board-with-a-yocto-os-and-kubernetes-on-top-best-practicies/255710)
**Author:** [@alessandro14](https://forums.developer.nvidia.com/u/alessandro14)\ **Replies:** 1\ **Last updated:** [June 7, 2023, 12:12am UTC](https://forums.developer.nvidia.com/t/xavier-board-with-a-yocto-os-and-kubernetes-on-top-best-practicies/255710 "2023-06-07T00:12:46Z")
Hello together We are building a Yocto Linux (BaseOS) for the Jetson Xavier and wanted to know what the best practices are regarding nvidia libraries in combination with kubernetes (k3s / containerd). During the develo… --- ## [Maximum Number of Warps and Warp Size per SM](https://forums.developer.nvidia.com/t/maximum-number-of-warps-and-warp-size-per-sm/234378)
**Author:** [@CUDANT](https://forums.developer.nvidia.com/u/CUDANT)\ **Replies:** 4\ **Last updated:** [November 16, 2022, 6:38pm UTC](https://forums.developer.nvidia.com/t/maximum-number-of-warps-and-warp-size-per-sm/234378 "2022-11-16T18:38:47Z")
Hi, I’d like to make sure of my understanding about the max number of warps and warp size per SM. Sorry for this naive question. For Pascal architecture (cc 6.1), according to Table 15 in CUDA C++ Programming Guide, each… --- ## [A few questions about BVH traversal engine and triangle intersection engine](https://forums.developer.nvidia.com/t/a-few-questions-about-bvh-traversal-engine-and-triangle-intersection-engine/233412)
**Author:** [@elapsestars](https://forums.developer.nvidia.com/u/elapsestars)\ **Replies:** 1\ **Last updated:** [November 10, 2022, 1:18pm UTC](https://forums.developer.nvidia.com/t/a-few-questions-about-bvh-traversal-engine-and-triangle-intersection-engine/233412 "2022-11-10T13:18:28Z")
Hello, I’m doing some study on ampere architecture and am a little confused about two engines ampere architecture uses (BVH traversal engine and triangle intersection engine). here are my questions: Can these two en… --- ## [\[Question\] Per-Thread Program Counters](https://forums.developer.nvidia.com/t/question-per-thread-program-counters/208716)
**Author:** [@congld92](https://forums.developer.nvidia.com/u/congld92)\ **Replies:** 4\ **Last updated:** [March 19, 2022, 11:02am UTC](https://forums.developer.nvidia.com/t/question-per-thread-program-counters/208716 "2022-03-19T11:02:10Z")
Hi friends, I am studying about GPU programming and when I learn about GPU compute capability, there is the sentence in NVIDIA TESLA V100 GPU ARCHITECTURE document: “The per-thread program counter (PC) that forms part o… --- ## [How do CUPTI Event Instances and Domains relate to hardware architecture?](https://forums.developer.nvidia.com/t/how-do-cupti-event-instances-and-domains-relate-to-hardware-architecture/188533)
**Author:** [@mrwolf](https://forums.developer.nvidia.com/u/mrwolf)\ **Replies:** 0\ **Last updated:** [September 6, 2021, 2:08pm UTC](https://forums.developer.nvidia.com/t/how-do-cupti-event-instances-and-domains-relate-to-hardware-architecture/188533 "2021-09-06T14:08:13Z")
Hi everyone. I have a Jetson AGX Xavier with a 512-core Volta GPU. I developed a CUPTI-based profiler to study the behavior of the GPU under specific workloads; for each benchmark, it profiles all events exposed by the…