# \#level2 **URL:** https://forums.developer.nvidia.com/tag/level2/1129.md [Latest](https://forums.developer.nvidia.com/latest.md) · [Categories](https://forums.developer.nvidia.com/categories.md) · [Tags](https://forums.developer.nvidia.com/tags.md) --- ## [Phy 2 Phy Connection From Orin Nano?](https://forums.developer.nvidia.com/t/phy-2-phy-connection-from-orin-nano/352601)
**Author:** [@chrisvsbender](https://forums.developer.nvidia.com/u/chrisvsbender)\ **Replies:** 4\ **Last updated:** [December 2, 2025, 10:45pm UTC](https://forums.developer.nvidia.com/t/phy-2-phy-connection-from-orin-nano/352601 "2025-12-02T22:45:37Z")
We are currently developing a Ethernet-switch expansion board for the NVIDIA Jetson Orin Nano. The device is intended to work by connecting an external base100t switch IC with internal PHYs (KSZ8895MLIX) to the ethernet… --- ## [Jetson Orin NX - PCIe TX Signal Strength Tuning](https://forums.developer.nvidia.com/t/jetson-orin-nx-pcie-tx-signal-strength-tuning/348722)
**Author:** [@che.cheng](https://forums.developer.nvidia.com/u/che.cheng)\ **Replies:** 20\ **Last updated:** [December 2, 2025, 4:16am UTC](https://forums.developer.nvidia.com/t/jetson-orin-nx-pcie-tx-signal-strength-tuning/348722 "2025-12-02T04:16:51Z")
Hi, We are performing environmental temperature testing on Jetson Orin NX with PCIe Gen4 NVMe storage at 70°C. During testing, we observed AER (Advanced Error Reporting) corrected errors on the PCIe link: pcieport 0004… --- ## [Loud switching / coil whine noise on Jetson Orin Nano during inference](https://forums.developer.nvidia.com/t/loud-switching-coil-whine-noise-on-jetson-orin-nano-during-inference/347298)
**Author:** [@chrisvsbender](https://forums.developer.nvidia.com/u/chrisvsbender)\ **Replies:** 4\ **Last updated:** [December 2, 2025, 3:42am UTC](https://forums.developer.nvidia.com/t/loud-switching-coil-whine-noise-on-jetson-orin-nano-during-inference/347298 "2025-12-02T03:42:33Z")
I have been struggling with this issue for a while and was hoping for some insight. It seems this question is related to this post, which does not have a conclusive answer. I am using Jetson Orin 8GB modules and a Nvidi… --- ## [SYS\_VIN\_HV and SYS\_VIN\_MV Absolute Maximum Ratings](https://forums.developer.nvidia.com/t/sys-vin-hv-and-sys-vin-mv-absolute-maximum-ratings/348473)
**Author:** [@willy.hsu](https://forums.developer.nvidia.com/u/willy.hsu)\ **Replies:** 1\ **Last updated:** [November 11, 2025, 1:05am UTC](https://forums.developer.nvidia.com/t/sys-vin-hv-and-sys-vin-mv-absolute-maximum-ratings/348473 "2025-11-11T01:05:05Z")
Hi Nvidia Engineers, While evaluating the power specifications, we noticed the descriptions in your design guide regarding the Absolute Maximum Ratings of SYS\_VIN\_HV and SYS\_VIN\_MV. Could you please confirm whether the… --- ## [MGBE REFCLK oscillator suggestion - AGX ORIN SOM](https://forums.developer.nvidia.com/t/mgbe-refclk-oscillator-suggestion-agx-orin-som/347286)
**Author:** [@syed.zameerbasha](https://forums.developer.nvidia.com/u/syed.zameerbasha)\ **Replies:** 10\ **Last updated:** [November 8, 2025, 10:16am UTC](https://forums.developer.nvidia.com/t/mgbe-refclk-oscillator-suggestion-agx-orin-som/347286 "2025-11-08T10:16:49Z")
Hi Team, we are designing AGX Orin based carrier board design, we need the MGBE Refclk oscillator 156.25MHZ suggested part numbers to use. The MGBE ref clk 156.25MHzs used in AGX orin devkit Schematic is not orderable … --- ## [Jetson Orin Nano 8GB - Lowest Theoretical Operating Power Consumption](https://forums.developer.nvidia.com/t/jetson-orin-nano-8gb-lowest-theoretical-operating-power-consumption/348662)
**Author:** [@hsmith](https://forums.developer.nvidia.com/u/hsmith)\ **Replies:** 15\ **Last updated:** [November 7, 2025, 2:30am UTC](https://forums.developer.nvidia.com/t/jetson-orin-nano-8gb-lowest-theoretical-operating-power-consumption/348662 "2025-11-07T02:30:24Z")
Hello, I recently have been experimenting with a Jetson Orin Nano 8GB Developer Kit, with the goal of running it with the lowest possible power consumption in an effort to maximize the battery life of our system. For s… --- ## [RoCE communication over MGBE on Thor](https://forums.developer.nvidia.com/t/roce-communication-over-mgbe-on-thor/348435)
**Author:** [@eezstreet](https://forums.developer.nvidia.com/u/eezstreet)\ **Replies:** 5\ **Last updated:** [November 6, 2025, 4:27pm UTC](https://forums.developer.nvidia.com/t/roce-communication-over-mgbe-on-thor/348435 "2025-11-06T16:27:41Z")
Hello. My understanding is that the Holoscan Sensor Bridge makes use of RDMA over Converged Ethernet with the Thor over its MGBE interfaces to drive ultra low latency communication with Camera over Ethernet. However - i… --- ## [Jetson Orin Nano (8GB L4T 36.3) Not booting up](https://forums.developer.nvidia.com/t/jetson-orin-nano-8gb-l4t-36-3-not-booting-up/346833)
**Author:** [@varunrajafr](https://forums.developer.nvidia.com/u/varunrajafr)\ **Replies:** 17\ **Last updated:** [November 5, 2025, 6:27am UTC](https://forums.developer.nvidia.com/t/jetson-orin-nano-8gb-l4t-36-3-not-booting-up/346833 "2025-11-05T06:27:58Z")
This issue popped up out of nowhere when I started to boot up my device, the power LED turns on for roughly 5 seconds before turning off. These are the bootlog that I’ve managed to get. Can anybody help me on resolving t… --- ## [Agx orin USB SI 测试工具问题](https://forums.developer.nvidia.com/t/agx-orin-usb-si/349520)
**Author:** [@dcb0223](https://forums.developer.nvidia.com/u/dcb0223)\ **Replies:** 6\ **Last updated:** [November 4, 2025, 9:59am UTC](https://forums.developer.nvidia.com/t/agx-orin-usb-si/349520 "2025-11-04T09:59:48Z")
Jetson\_TX1\_USB\_SS\_Compliance\_Test\_Guide\_AN.pdf (1.1 MB) Jetson\_TX2\_TX2i\_USB\_SS\_Compliance\_Testing\_Guide\_Application\_Note.pdf (1.1 MB) Jetson\_TX1\_USB\_SS\_Compliance\_Test\_Guide\_AN.pdf (1.1 MB) 关于USB2.0的SI测试工具，我找到这3个文档，以及… --- ## [Critical Issue: Unable to set GPIO Output (Always 0V) on Jetson Nano - Tested multiple Pins & Methods](https://forums.developer.nvidia.com/t/critical-issue-unable-to-set-gpio-output-always-0v-on-jetson-nano-tested-multiple-pins-methods/349144)
**Author:** [@b.dejong1](https://forums.developer.nvidia.com/u/b.dejong1)\ **Replies:** 9\ **Last updated:** [November 3, 2025, 6:32am UTC](https://forums.developer.nvidia.com/t/critical-issue-unable-to-set-gpio-output-always-0v-on-jetson-nano-tested-multiple-pins-methods/349144 "2025-11-03T06:32:38Z")
Hello Jetson community and NVIDIA support, I am experiencing a critical issue where I am unable to programmatically control any standard GPIO output pin on my Jetson Nano. The output voltage consistently reads 0V with a… --- ## [MGBE SGMII 2.5G Link](https://forums.developer.nvidia.com/t/mgbe-sgmii-2-5g-link/349422)
**Author:** [@miquel.sole](https://forums.developer.nvidia.com/u/miquel.sole)\ **Replies:** 5\ **Last updated:** [October 31, 2025, 7:13pm UTC](https://forums.developer.nvidia.com/t/mgbe-sgmii-2-5g-link/349422 "2025-10-31T19:13:57Z")
Hi, We are currently deploying an NVIDIA Jetson Orin module on a custom carrier board and are facing some issues when bringing up the network interfaces. We have connected the Jetson Orin’s MGBE interface to an SGMII i… --- ## [Discrepancy in CPHY Pin Mapping Documentation - Jetson Thor Design Guide](https://forums.developer.nvidia.com/t/discrepancy-in-cphy-pin-mapping-documentation-jetson-thor-design-guide/348896)
**Author:** [@norman\_xu](https://forums.developer.nvidia.com/u/norman_xu)\ **Replies:** 14\ **Last updated:** [October 31, 2025, 10:06am UTC](https://forums.developer.nvidia.com/t/discrepancy-in-cphy-pin-mapping-documentation-jetson-thor-design-guide/348896 "2025-10-31T10:06:12Z")
Hello Nvidia, I have identified a discrepancy in the CPHY pin connections documented in the Jetson Thor Series Modules Design Guide (DG12084001\_v1.2.pdf). Documented Pin Connections: Figure 10-2. Camera CSI C-PHY Con… --- ## [Jetson Orin NX 16G CSI Pinout](https://forums.developer.nvidia.com/t/jetson-orin-nx-16g-csi-pinout/349380)
**Author:** [@mgamota2](https://forums.developer.nvidia.com/u/mgamota2)\ **Replies:** 4\ **Last updated:** [October 30, 2025, 5:46pm UTC](https://forums.developer.nvidia.com/t/jetson-orin-nx-16g-csi-pinout/349380 "2025-10-30T17:46:38Z")
I have designed a custom board which has 2 22-pin CSI outputs and I want to interface it with a Jetson Orin NX 16G. I am a new user so I can only include 1 image, I am happy to provide more. In the image below is the bo… --- ## [Cannot use 10Gb SFP+ port: Failed to get PCS block lock](https://forums.developer.nvidia.com/t/cannot-use-10gb-sfp-port-failed-to-get-pcs-block-lock/349493)
**Author:** [@henry74](https://forums.developer.nvidia.com/u/henry74)\ **Replies:** 1\ **Last updated:** [October 30, 2025, 10:50am UTC](https://forums.developer.nvidia.com/t/cannot-use-10gb-sfp-port-failed-to-get-pcs-block-lock/349493 "2025-10-30T10:50:39Z")
Platform: Jetson AGX Orin JetPack version: 6.2.1 Carrier board: Forecr DSBOARD-AGXMAX Issue: SFP+ port (sfp0) fails to come up with PCS block lock error I’m trying to use the SFP+ port on the DSBOARD-AGXMAX carrier b… --- ## [JETPACK5.1.5使用HDMI无法显示](https://forums.developer.nvidia.com/t/jetpack5-1-5-hdmi/349120)
**Author:** [@2799029655](https://forums.developer.nvidia.com/u/2799029655)\ **Replies:** 33\ **Last updated:** [October 29, 2025, 4:02pm UTC](https://forums.developer.nvidia.com/t/jetpack5-1-5-hdmi/349120 "2025-10-29T16:02:16Z")
我们自研的板子使用的HDMI，参考了文档配置成HDMI显示的，更改的内容如下 1、更改PINMUX 2、按照https://forums.developer.nvidia.com/t/hdmi-display-does-not-work-after-update-to-jetpack-5-0-2/226581/26修改了如下内容 3、HDMI DCB 4、重新烧录系统后执行 请教下，哪里更改的有问题… --- ## [AQR113C 10G Ethernet PHY of AGX Orin devkit -clock oscillator](https://forums.developer.nvidia.com/t/aqr113c-10g-ethernet-phy-of-agx-orin-devkit-clock-oscillator/349328)
**Author:** [@syed.zameerbasha](https://forums.developer.nvidia.com/u/syed.zameerbasha)\ **Replies:** 1\ **Last updated:** [October 29, 2025, 10:24am UTC](https://forums.developer.nvidia.com/t/aqr113c-10g-ethernet-phy-of-agx-orin-devkit-clock-oscillator/349328 "2025-10-29T10:24:58Z")
Hi Team, we are using 10G ethernet PHY(AQR113C) with external magnetics and connector in our AGX Orin based carrier board, we need to know any recommended part number for the 156.25MHZ MGBE clock oscillator, we have ch… --- ## [原来图中的FAN\_PWM对设备树中的PWM那个节点,?](https://forums.developer.nvidia.com/t/fan-pwm-pwm/349252)
**Author:** [@jeremyzhang](https://forums.developer.nvidia.com/u/jeremyzhang)\ **Replies:** 3\ **Last updated:** [October 29, 2025, 2:08am UTC](https://forums.developer.nvidia.com/t/fan-pwm-pwm/349252 "2025-10-29T02:08:00Z")
背景:orin nx 16, jetpack6.2.1,自研底板 FAN\_PWM是从核心板过来的, 在默认的设备树中,用的是pwm3: tegra234-p3768-0000.dtsi pwm@32a0000 { assigned-clocks = \<&bpmp TEGRA234\_CLK\_PWM3\>; assigned-cl… --- ## [Jetson T5000 mgbe + aqr113c phy dts 如何配置](https://forums.developer.nvidia.com/t/jetson-t5000-mgbe-aqr113c-phy-dts/348716)
**Author:** [@feiniao08102](https://forums.developer.nvidia.com/u/feiniao08102)\ **Replies:** 3\ **Last updated:** [October 28, 2025, 8:03am UTC](https://forums.developer.nvidia.com/t/jetson-t5000-mgbe-aqr113c-phy-dts/348716 "2025-10-28T08:03:47Z")
自己做的底板 jetson\_r38.2.1 dts 做如下修改，获取不到ip地址。但是移除 phy-handle = \<&mgbe0\_aqr113c\_phy\>; 则可以获取到ip地址 /\* MGBE 0 \*/ mgbe0: ethernet@a808a10000 { status = "okay"; … --- ## [Queries regarding power consumption of Thor T5000 module](https://forums.developer.nvidia.com/t/queries-regarding-power-consumption-of-thor-t5000-module/348819)
**Author:** [@abhi.choksi](https://forums.developer.nvidia.com/u/abhi.choksi)\ **Replies:** 1\ **Last updated:** [October 27, 2025, 6:57pm UTC](https://forums.developer.nvidia.com/t/queries-regarding-power-consumption-of-thor-t5000-module/348819 "2025-10-27T18:57:31Z")
Hi, I am working on a project to design carrier board for Nvidia Jetson AGX Thor T5000 module. I have some queries regarding its power consumption and power budget design which are as below. In datasheet of T5000 modu… --- ## [Can I set UART1\_TX to GPIO input mode on Jetson AGX Orin](https://forums.developer.nvidia.com/t/can-i-set-uart1-tx-to-gpio-input-mode-on-jetson-agx-orin/349004)
**Author:** [@jacobe.zang](https://forums.developer.nvidia.com/u/jacobe.zang)\ **Replies:** 4\ **Last updated:** [October 27, 2025, 9:12am UTC](https://forums.developer.nvidia.com/t/can-i-set-uart1-tx-to-gpio-input-mode-on-jetson-agx-orin/349004 "2025-10-27T09:12:10Z")
On the Jetson AGX Orin platform, I’m trying to multiplex the UART TX pin into standard GPIO mode and set it to input mode to read external digital signals. I’m experiencing an inconsistency: UART5\_TX (Pin X): I succes… --- ## [Unable to set gpio pins as pull up](https://forums.developer.nvidia.com/t/unable-to-set-gpio-pins-as-pull-up/347557)
**Author:** [@daniel.gonzalez3](https://forums.developer.nvidia.com/u/daniel.gonzalez3)\ **Replies:** 9\ **Last updated:** [October 27, 2025, 7:56am UTC](https://forums.developer.nvidia.com/t/unable-to-set-gpio-pins-as-pull-up/347557 "2025-10-27T07:56:23Z")
Hi, I am using a device tree overlay applied with jetson-io to enable gpio pins as input/output and with pull up or down. I was able to set pin 13 from pwm to input and two other pins to output. Other pins are already se… --- ## [Control several ethernet interfaces with Thor](https://forums.developer.nvidia.com/t/control-several-ethernet-interfaces-with-thor/347067)
**Author:** [@harald.ilg](https://forums.developer.nvidia.com/u/harald.ilg)\ **Replies:** 3\ **Last updated:** [October 23, 2025, 4:36pm UTC](https://forums.developer.nvidia.com/t/control-several-ethernet-interfaces-with-thor/347067 "2025-10-23T16:36:48Z")
Hy, In a customer project, we are tasked with creating a motherboard for a Jetson Thor Series module. Three separate Ethernet interfaces are to be available: Standard 1000 Base TX with RJ 45 connector for direct conne… --- ## [Force-Recovery fails with Xavier NX](https://forums.developer.nvidia.com/t/force-recovery-fails-with-xavier-nx/346048)
**Author:** [@andreas.brinkhaus](https://forums.developer.nvidia.com/u/andreas.brinkhaus)\ **Replies:** 21\ **Last updated:** [October 23, 2025, 1:44pm UTC](https://forums.developer.nvidia.com/t/force-recovery-fails-with-xavier-nx/346048 "2025-10-23T13:44:20Z")
Hello together, I have the issue that I can’t bring two Xavier NX SOMs in Force-Recovery mode. My setup is a Jetson Nano Devkit, connected with USB to my flashing PC and to UART. The Force-Recovery is permanently conne… --- ## [AGX ORIN调试SPI信号异常](https://forums.developer.nvidia.com/t/agx-orin-spi/348458)
**Author:** [@chutianwei](https://forums.developer.nvidia.com/u/chutianwei)\ **Replies:** 12\ **Last updated:** [October 23, 2025, 1:27pm UTC](https://forums.developer.nvidia.com/t/agx-orin-spi/348458 "2025-10-23T13:27:21Z")
我用Jetson AGX Orin™ Developer Kit调试SPI1接口。配置步骤如下 jetson-io配置spi的pinmux，配置完之后用busybox devmem验证 修改SPI频率 用echo “12312435443523412“ | spi-pipe -d /dev/spidev0.0 命令行验证输出，示波器抓取波形验证不符合预期 请帮忙分析原因~谢谢~ --- ## [The AGX Orin module uses lane 6 of the PCIe C4 controller as x1](https://forums.developer.nvidia.com/t/the-agx-orin-module-uses-lane-6-of-the-pcie-c4-controller-as-x1/348606)
**Author:** [@2529495525](https://forums.developer.nvidia.com/u/2529495525)\ **Replies:** 3\ **Last updated:** [October 23, 2025, 11:29am UTC](https://forums.developer.nvidia.com/t/the-agx-orin-module-uses-lane-6-of-the-pcie-c4-controller-as-x1/348606 "2025-10-23T11:29:05Z")
Currently, we are using our own custom board in combination with the AGX Orin module. There is an i226 network card interface with PCIe x1, which we have connected to lane 6 of the PCIe C4 controller on the Orin module. … --- ## [Regarding to the MIPI DSI and CSI signal routing requirementon on Jetson TX2 NX product design guide](https://forums.developer.nvidia.com/t/regarding-to-the-mipi-dsi-and-csi-signal-routing-requirementon-on-jetson-tx2-nx-product-design-guide/346955)
**Author:** [@katsuya.yamamoto](https://forums.developer.nvidia.com/u/katsuya.yamamoto)\ **Replies:** 7\ **Last updated:** [October 23, 2025, 7:05am UTC](https://forums.developer.nvidia.com/t/regarding-to-the-mipi-dsi-and-csi-signal-routing-requirementon-on-jetson-tx2-nx-product-design-guide/346955 "2025-10-23T07:05:18Z")
Hi all, Let me ask a question regarding to the item of “Max trace delay skew between DQ and CLK” in 7.1.1 MIPI DSI and CSI Design Guidelines. The requirement of this is 5ps. But As for the MIPI D-phy specification (v1.… --- ## [Orin Nano board can not power on again if run poweroff command to power off Nano Board](https://forums.developer.nvidia.com/t/orin-nano-board-can-not-power-on-again-if-run-poweroff-command-to-power-off-nano-board/348594)
**Author:** [@meng.li](https://forums.developer.nvidia.com/u/meng.li)\ **Replies:** 14\ **Last updated:** [October 23, 2025, 5:48am UTC](https://forums.developer.nvidia.com/t/orin-nano-board-can-not-power-on-again-if-run-poweroff-command-to-power-off-nano-board/348594 "2025-10-23T05:48:58Z")
I download jetpack 6.2, linux 36.4.3. And then burn NVIDAI Orin Nano development board. After system boots up completely, I run “sudo poweroff -p“ command in console, and then turn off power switch. But when I turn on… --- ## [UHP, HP, HQ vs V4L2\_ENC\_HW\_PRESET\_XXX](https://forums.developer.nvidia.com/t/uhp-hp-hq-vs-v4l2-enc-hw-preset-xxx/348362)
**Author:** [@oviano](https://forums.developer.nvidia.com/u/oviano)\ **Replies:** 5\ **Last updated:** [October 22, 2025, 9:18am UTC](https://forums.developer.nvidia.com/t/uhp-hp-hq-vs-v4l2-enc-hw-preset-xxx/348362 "2025-10-22T09:18:24Z")
Would it be correct to assume that UHP = V4L2\_ENC\_HW\_PRESET\_ULTRAFAST HP = V4L2\_ENC\_HW\_PRESET\_FAST HQ = V4L2\_ENC\_HW\_PRESET\_SLOW When looking at the chart on page 15 below vs the API definitions? Perhaps you can make… --- ## [How to using CSI1 CLK?](https://forums.developer.nvidia.com/t/how-to-using-csi1-clk/345776)
**Author:** [@MDS\_Eddy](https://forums.developer.nvidia.com/u/MDS_Eddy)\ **Replies:** 4\ **Last updated:** [October 21, 2025, 7:41am UTC](https://forums.developer.nvidia.com/t/how-to-using-csi1-clk/345776 "2025-10-21T07:41:48Z")
We designed our custom board for Orin NX. It has to use CSI0 ~ CSI3 for each 4 devices. CSI1\_CLK doesn’t works and the others(0, 2, 3) is working well. It is notified to set RSVD in documentation and Pinmux table. Ho… --- ## [RGMII\_SMA\_MDIO and RGMII\_SMA\_MDC config as gpio but out of control](https://forums.developer.nvidia.com/t/rgmii-sma-mdio-and-rgmii-sma-mdc-config-as-gpio-but-out-of-control/347516)
**Author:** [@zw0](https://forums.developer.nvidia.com/u/zw0)\ **Replies:** 21\ **Last updated:** [October 21, 2025, 3:40am UTC](https://forums.developer.nvidia.com/t/rgmii-sma-mdio-and-rgmii-sma-mdc-config-as-gpio-but-out-of-control/347516 "2025-10-21T03:40:19Z")
Basic Info: hardware: jetson-agx-orin-devkit JetPack : 6.2 Jetson Linux : 36.4.3 I config below two pin E7 and E6 to gpio mode, but using multimeter measure the value is low also try using gpioset to pull up the … [Next page](https://forums.developer.nvidia.com/tag/level2/1129.md?match_all_tags=true&page=1&tags%5B%5D=level2)