Loading library from ./libsampleTRTLib.so
Running test ...
nvinfer: Registered plugin creator - ::GridAnchor_TRT version 1
nvinfer: Registered plugin creator - ::NMS_TRT version 1
nvinfer: Registered plugin creator - ::Reorg_TRT version 1
nvinfer: Registered plugin creator - ::Region_TRT version 1
nvinfer: Registered plugin creator - ::Clip_TRT version 1
nvinfer: Registered plugin creator - ::LReLU_TRT version 1
nvinfer: Registered plugin creator - ::PriorBox_TRT version 1
nvinfer: Registered plugin creator - ::Normalize_TRT version 1
nvinfer: Registered plugin creator - ::RPROI_TRT version 1
nvinfer: Registered plugin creator - ::BatchedNMS_TRT version 1
nvinfer: Registered plugin creator - ::FlattenConcat_TRT version 1
nvinfer: Registered plugin creator - ::CropAndResize version 1
nvinfer: Registered plugin creator - ::DetectionLayer_TRT version 1
nvinfer: Registered plugin creator - ::Proposal version 1
nvinfer: Registered plugin creator - ::ProposalLayer_TRT version 1
nvinfer: Registered plugin creator - ::PyramidROIAlign_TRT version 1
nvinfer: Registered plugin creator - ::ResizeNearest_TRT version 1
nvinfer: Registered plugin creator - ::Split version 1
nvinfer: Registered plugin creator - ::SpecialSlice_TRT version 1
nvinfer: Registered plugin creator - ::InstanceNormalization_TRT version 1
nvinfer: Applying generic optimizations to the graph for inference.
nvinfer: Original: 101 layers
nvinfer: After dead-layer removal: 101 layers
nvinfer: Fusing conv4_3_norm_mbox_loc_perm with conv4_3_norm_mbox_loc_flat
nvinfer: Fusing conv4_3_norm_mbox_conf_perm with conv4_3_norm_mbox_conf_flat
nvinfer: Fusing fc7_mbox_loc_perm with fc7_mbox_loc_flat
nvinfer: Fusing fc7_mbox_conf_perm with fc7_mbox_conf_flat
nvinfer: Fusing conv6_2_mbox_loc_perm with conv6_2_mbox_loc_flat
nvinfer: Fusing conv6_2_mbox_conf_perm with conv6_2_mbox_conf_flat
nvinfer: Fusing conv7_2_mbox_loc_perm with conv7_2_mbox_loc_flat
nvinfer: Fusing conv7_2_mbox_conf_perm with conv7_2_mbox_conf_flat
nvinfer: Fusing conv8_2_mbox_loc_perm with conv8_2_mbox_loc_flat
nvinfer: Fusing conv8_2_mbox_conf_perm with conv8_2_mbox_conf_flat
nvinfer: Fusing conv9_2_mbox_loc_perm with conv9_2_mbox_loc_flat
nvinfer: Fusing conv9_2_mbox_conf_perm with conv9_2_mbox_conf_flat
nvinfer: After Myelin optimization: 89 layers
nvinfer: After scale fusion: 89 layers
nvinfer: Fusing conv1_1 with relu1_1
nvinfer: Fusing conv1_2 with relu1_2
nvinfer: Fusing conv2_1 with relu2_1
nvinfer: Fusing conv2_2 with relu2_2
nvinfer: Fusing conv3_1 with relu3_1
nvinfer: Fusing conv3_2 with relu3_2
nvinfer: Fusing conv3_3 with relu3_3
nvinfer: Fusing conv4_1 with relu4_1
nvinfer: Fusing conv4_2 with relu4_2
nvinfer: Fusing conv4_3 with relu4_3
nvinfer: Fusing conv5_1 with relu5_1
nvinfer: Fusing conv5_2 with relu5_2
nvinfer: Fusing conv5_3 with relu5_3
nvinfer: Fusing fc6 with relu6
nvinfer: Fusing fc7 with relu7
nvinfer: Fusing conv6_1 with conv6_1_relu
nvinfer: Fusing conv6_2 with conv6_2_relu
nvinfer: Fusing conv7_1 with conv7_1_relu
nvinfer: Fusing conv7_2 with conv7_2_relu
nvinfer: Fusing conv8_1 with conv8_1_relu
nvinfer: Fusing conv8_2 with conv8_2_relu
nvinfer: Fusing conv9_1 with conv9_1_relu
nvinfer: Fusing conv9_2 with conv9_2_relu
nvinfer: After vertical fusions: 66 layers
nvinfer: After final dead-layer removal: 66 layers
nvinfer: Merging layers: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf
nvinfer: Merging layers: fc7_mbox_loc || fc7_mbox_conf
nvinfer: Merging layers: conv6_2_mbox_loc || conv6_2_mbox_conf
nvinfer: Merging layers: conv7_2_mbox_loc || conv7_2_mbox_conf
nvinfer: Merging layers: conv8_2_mbox_loc || conv8_2_mbox_conf
nvinfer: Merging layers: conv9_2_mbox_loc || conv9_2_mbox_conf
nvinfer: After tensor merging: 60 layers
nvinfer: Eliminating concatenation mbox_loc
nvinfer: Retargeting conv4_3_norm_mbox_loc_flat to mbox_loc
nvinfer: Retargeting fc7_mbox_loc_flat to mbox_loc
nvinfer: Retargeting conv6_2_mbox_loc_flat to mbox_loc
nvinfer: Retargeting conv7_2_mbox_loc_flat to mbox_loc
nvinfer: Retargeting conv8_2_mbox_loc_flat to mbox_loc
nvinfer: Retargeting conv9_2_mbox_loc_flat to mbox_loc
nvinfer: Eliminating concatenation mbox_priorbox
nvinfer: Generating copy for conv4_3_norm_mbox_priorbox to mbox_priorbox
nvinfer: Generating copy for fc7_mbox_priorbox to mbox_priorbox
nvinfer: Generating copy for conv6_2_mbox_priorbox to mbox_priorbox
nvinfer: Generating copy for conv7_2_mbox_priorbox to mbox_priorbox
nvinfer: Generating copy for conv8_2_mbox_priorbox to mbox_priorbox
nvinfer: Generating copy for conv9_2_mbox_priorbox to mbox_priorbox
nvinfer: Eliminating concatenation mbox_conf
nvinfer: Generating copy for conv4_3_norm_mbox_conf_flat to mbox_conf
nvinfer: Generating copy for fc7_mbox_conf_flat to mbox_conf
nvinfer: Generating copy for conv6_2_mbox_conf_flat to mbox_conf
nvinfer: Generating copy for conv7_2_mbox_conf_flat to mbox_conf
nvinfer: Generating copy for conv8_2_mbox_conf_flat to mbox_conf
nvinfer: Generating copy for conv9_2_mbox_conf_flat to mbox_conf
nvinfer: After concat removal: 69 layers
nvinfer: Graph construction and optimization completed in 0.0319176 seconds.
nvinfer: 
nvinfer: --------------- Layers running on DLA: 
nvinfer: 
nvinfer: --------------- Layers running on GPU: 
nvinfer: conv1_1 + relu1_1, conv1_2 + relu1_2, pool1, conv2_1 + relu2_1, conv2_2 + relu2_2, pool2, conv3_1 + relu3_1, conv3_2 + relu3_2, conv3_3 + relu3_3, pool3, conv4_1 + relu4_1, conv4_2 + relu4_2, conv4_3 + relu4_3, conv4_3_norm, conv4_3_norm_mbox_priorbox, conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf, pool4, conv5_1 + relu5_1, conv5_2 + relu5_2, conv5_3 + relu5_3, pool5, fc6 + relu6, fc7 + relu7, fc7_mbox_priorbox, fc7_mbox_loc || fc7_mbox_conf, conv6_1 + conv6_1_relu, conv6_2 + conv6_2_relu, conv6_2_mbox_priorbox, conv6_2_mbox_loc || conv6_2_mbox_conf, conv7_1 + conv7_1_relu, conv7_2 + conv7_2_relu, conv7_2_mbox_priorbox, conv7_2_mbox_loc || conv7_2_mbox_conf, conv8_1 + conv8_1_relu, conv8_2 + conv8_2_relu, conv8_2_mbox_priorbox, conv8_2_mbox_loc || conv8_2_mbox_conf, conv9_1 + conv9_1_relu, conv9_2 + conv9_2_relu, conv9_2_mbox_priorbox, conv9_2_mbox_loc || conv9_2_mbox_conf, conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat, fc7_mbox_loc_perm + fc7_mbox_loc_flat, conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat, conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat, conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat, conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat, conv4_3_norm_mbox_priorbox copy, fc7_mbox_priorbox copy, conv6_2_mbox_priorbox copy, conv7_2_mbox_priorbox copy, conv8_2_mbox_priorbox copy, conv9_2_mbox_priorbox copy, conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat, fc7_mbox_conf_perm + fc7_mbox_conf_flat, conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat, conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat, conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat, conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat, conv4_3_norm_mbox_conf_flat copy, fc7_mbox_conf_flat copy, conv6_2_mbox_conf_flat copy, conv7_2_mbox_conf_flat copy, conv8_2_mbox_conf_flat copy, conv9_2_mbox_conf_flat copy, mbox_conf_reshape, mbox_conf_softmax, mbox_conf_flatten, detection_out, 
nvinfer: Constructing optimization profile number 0 [1/1].
nvinfer: *************** Autotuning format combination: Float(1,300,90000,270000) -> Float(1,300,90000,5760000) ***************
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv1_1 + relu1_1 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv1_1 + relu1_1 (CaskConvolution)
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 2.09222
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 7.27008
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 1.61408
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 3.22112
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 1.61066
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 5.01584
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 1.61488
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 7.21488
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 3.16768
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 7.30902
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 2.26352
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 2.06368
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 7.27571
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 5.08736
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 3.07674
nvinfer: Fastest Tactic: 5137655947464784826 Time: 1.61066
nvinfer: --------------- Timing Runner: conv1_1 + relu1_1 (CudaConvolution)
nvinfer: Tactic: 0 time 9.36298
nvinfer: Tactic: 2 time 10.2014
nvinfer: Tactic: 5 time 67.1027
nvinfer: Tactic: 6 time 9.68112
nvinfer: Tactic: 57 time 6.39536
nvinfer: Fastest Tactic: 57 Time: 6.39536
nvinfer: --------------- Timing Runner: conv1_1 + relu1_1 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 5137655947464784826
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: 
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,300,90000,5760000) -> Float(1,300,90000,5760000) ***************
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv1_2 + relu1_2 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv1_2 + relu1_2 (CaskConvolution)
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 18.1052
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 18.0616
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 14.9316
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 27.9886
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 14.4025
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 12.0586
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 14.8181
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 18.1261
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 28.2646
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 18.4971
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 18.701
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 16.7819
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 18.235
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 12.2452
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 27.4087
nvinfer: Fastest Tactic: 5921334924264294896 Time: 12.0586
nvinfer: --------------- Timing Runner: conv1_2 + relu1_2 (CudaConvolution)
nvinfer: Tactic: 0 time 37.3616
nvinfer: Tactic: 2 skipped. Scratch requested: 207360000, available: 104857600
nvinfer: Tactic: 5 time 132.209
nvinfer: Tactic: 6 time 16.1229
nvinfer: Tactic: 57 time 18.9954
nvinfer: Some tactics do not have sufficient workspace memory to run. Increasing workspace size may increase performance, please check verbose output.
nvinfer: Fastest Tactic: 6 Time: 16.1229
nvinfer: --------------- Timing Runner: conv1_2 + relu1_2 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 5921334924264294896
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: 
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv1_2 + relu1_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: *************** Autotuning format combination: Float(1,300,90000,5760000) -> Float(1,150,22500,1440000) ***************
nvinfer: --------------- Timing Runner: pool1 (Pooling)
nvinfer: Tactic: -1 time 1.21302
nvinfer: Fastest Tactic: -1 Time: 1.21302
nvinfer: --------------- Timing Runner: pool1 (TiledPooling)
nvinfer: Tactic: 5505281 time 2.32592
nvinfer: Tactic: 5570817 time 1.68474
nvinfer: Tactic: 5636353 time 1.44266
nvinfer: Tactic: 5701889 time 1.51526
nvinfer: Tactic: 5767425 time 1.57974
nvinfer: Tactic: 5832961 time 1.83344
nvinfer: Tactic: 5898497 time 1.56214
nvinfer: Tactic: 5964033 time 1.63904
nvinfer: Tactic: 6029569 time 2.77984
nvinfer: Tactic: 6095105 time 2.44186
nvinfer: Tactic: 6160641 time 2.45562
nvinfer: Tactic: 6226177 time 2.37814
nvinfer: Tactic: 6291713 time 2.42224
nvinfer: Tactic: 6357249 time 2.41664
nvinfer: Tactic: 6422785 time 2.37472
nvinfer: Tactic: 6488321 time 2.37744
nvinfer: Fastest Tactic: 5636353 Time: 1.44266
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: Pooling Tactic: -1
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,150,22500,1440000) -> Float(1,150,22500,2880000) ***************
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv2_1 + relu2_1 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv2_1 + relu2_1 (CaskConvolution)
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 8.9695
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 10.4463
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 7.5207
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 7.19088
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 7.19142
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 6.77574
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 7.3544
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 9.84218
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 7.52944
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 9.53408
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 9.34016
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 8.29466
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 9.95568
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 6.51562
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 7.11744
nvinfer: Fastest Tactic: -1343271414618805657 Time: 6.51562
nvinfer: --------------- Timing Runner: conv2_1 + relu2_1 (CudaConvolution)
nvinfer: Tactic: 0 time 17.141
nvinfer: Tactic: 2 time 17.8279
nvinfer: Tactic: 5 time 72.6581
nvinfer: Tactic: 6 time 8.60086
nvinfer: Tactic: 57 time 16.4688
nvinfer: Fastest Tactic: 6 Time: 8.60086
nvinfer: --------------- Timing Runner: conv2_1 + relu2_1 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv2_1 + relu2_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,150,22500,2880000) -> Float(1,150,22500,2880000) ***************
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv2_2 + relu2_2 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv2_2 + relu2_2 (CaskConvolution)
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 17.4511
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 18.1979
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 14.5134
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 14.1635
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 13.9986
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 11.9058
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 14.4699
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 18.2952
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 14.1423
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 17.8701
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 18.0405
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 16.0574
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 19.079
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 11.3346
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 13.7575
nvinfer: Fastest Tactic: -1343271414618805657 Time: 11.3346
nvinfer: --------------- Timing Runner: conv2_2 + relu2_2 (CudaConvolution)
nvinfer: Tactic: 0 time 29.7693
nvinfer: Tactic: 2 time 30.1731
nvinfer: Tactic: 5 time 105.845
nvinfer: Tactic: 6 time 14.7349
nvinfer: Tactic: 57 time 27.2759
nvinfer: Fastest Tactic: 6 Time: 14.7349
nvinfer: --------------- Timing Runner: conv2_2 + relu2_2 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv2_2 + relu2_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,150,22500,2880000) -> Float(1,75,5625,720000) ***************
nvinfer: --------------- Timing Runner: pool2 (Pooling)
nvinfer: Tactic: -1 time 0.65472
nvinfer: Fastest Tactic: -1 Time: 0.65472
nvinfer: --------------- Timing Runner: pool2 (TiledPooling)
nvinfer: Tactic: 5505281 time 1.35408
nvinfer: Tactic: 5570817 time 1.01536
nvinfer: Tactic: 5636353 time 1.2008
nvinfer: Tactic: 5701889 time 0.857216
nvinfer: Tactic: 5767425 time 0.77888
nvinfer: Tactic: 5832961 time 0.81856
nvinfer: Tactic: 5898497 time 1.00698
nvinfer: Tactic: 5964033 time 0.837184
nvinfer: Tactic: 6029569 time 1.2504
nvinfer: Tactic: 6095105 time 1.2177
nvinfer: Tactic: 6160641 time 1.05888
nvinfer: Tactic: 6226177 time 1.0513
nvinfer: Tactic: 6291713 time 1.10576
nvinfer: Tactic: 6357249 time 1.06784
nvinfer: Tactic: 6422785 time 1.00874
nvinfer: Tactic: 6488321 time 1.23494
nvinfer: Fastest Tactic: 5767425 Time: 0.77888
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: Pooling Tactic: -1
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,75,5625,720000) -> Float(1,75,5625,1440000) ***************
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv3_1 + relu3_1 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv3_1 + relu3_1 (CaskConvolution)
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 8.88896
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 9.1087
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 7.31654
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 7.07622
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 7.0431
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 5.90758
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 7.15446
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 8.67526
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 7.16182
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 8.36752
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 9.1808
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 8.09254
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 8.94134
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 5.57142
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 6.88042
nvinfer: Fastest Tactic: -1343271414618805657 Time: 5.57142
nvinfer: --------------- Timing Runner: conv3_1 + relu3_1 (CudaConvolution)
nvinfer: Tactic: 0 time 14.9626
nvinfer: Tactic: 2 time 13.5747
nvinfer: Tactic: 5 skipped. Scratch requested: 145948672, available: 104857600
nvinfer: Tactic: 6 time 6.84896
nvinfer: Tactic: 57 time 15.4497
nvinfer: Fastest Tactic: 6 Time: 6.84896
nvinfer: --------------- Timing Runner: conv3_1 + relu3_1 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv3_1 + relu3_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,75,5625,1440000) -> Float(1,75,5625,1440000) ***************
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv3_2 + relu3_2 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv3_2 + relu3_2 (CaskConvolution)
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 17.3478
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 16.485
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 14.3633
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 13.7525
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 13.79
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 10.6045
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 14.1889
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 16.58
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 13.8665
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 16.05
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 18.2227
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 15.9093
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 16.5109
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 10.0771
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 13.3651
nvinfer: Fastest Tactic: -1343271414618805657 Time: 10.0771
nvinfer: --------------- Timing Runner: conv3_2 + relu3_2 (CudaConvolution)
nvinfer: Tactic: 0 time 27.6364
nvinfer: Tactic: 2 time 24.8897
nvinfer: Tactic: 5 skipped. Scratch requested: 289669120, available: 104857600
nvinfer: Tactic: 6 time 11.7619
nvinfer: Tactic: 57 time 33.0083
nvinfer: Fastest Tactic: 6 Time: 11.7619
nvinfer: --------------- Timing Runner: conv3_2 + relu3_2 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv3_2 + relu3_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,75,5625,1440000) -> Float(1,75,5625,1440000) ***************
nvinfer: *************** Autotuning format combination: Float(1,75,5625,1440000) -> Float(1,38,1444,369664) ***************
nvinfer: --------------- Timing Runner: pool3 (Pooling)
nvinfer: Tactic: -1 time 0.86864
nvinfer: Fastest Tactic: -1 Time: 0.86864
nvinfer: --------------- Timing Runner: pool3 (TiledPooling)
nvinfer: Tactic: 5505281 time 0.854496
nvinfer: Tactic: 5570817 time 0.552
nvinfer: Tactic: 5636353 time 0.48272
nvinfer: Tactic: 5701889 time 0.50352
nvinfer: Tactic: 5767425 time 0.435904
nvinfer: Tactic: 5832961 time 0.479264
nvinfer: Tactic: 5898497 time 0.511616
nvinfer: Tactic: 5964033 time 0.46704
nvinfer: Tactic: 6029569 time 0.733984
nvinfer: Tactic: 6095105 time 0.52304
nvinfer: Tactic: 6160641 time 0.556256
nvinfer: Tactic: 6226177 time 0.6656
nvinfer: Tactic: 6291713 time 0.55936
nvinfer: Tactic: 6357249 time 0.6296
nvinfer: Tactic: 6422785 time 0.57984
nvinfer: Tactic: 6488321 time 0.609856
nvinfer: Fastest Tactic: 5767425 Time: 0.435904
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: TiledPooling Tactic: 5767425
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,38,1444,369664) -> Float(1,38,1444,739328) ***************
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv4_1 + relu4_1 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv4_1 + relu4_1 (CaskConvolution)
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 9.50906
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 8.79168
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 7.81446
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 7.5319
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 7.45462
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 6.13382
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 7.69946
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 9.18144
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 7.66288
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 8.77984
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 9.9593
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 8.49878
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 9.08352
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 5.66496
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 7.30096
nvinfer: Fastest Tactic: -1343271414618805657 Time: 5.66496
nvinfer: --------------- Timing Runner: conv4_1 + relu4_1 (CudaConvolution)
nvinfer: Tactic: 0 time 17.705
nvinfer: Tactic: 2 time 20.0689
nvinfer: Tactic: 5 skipped. Scratch requested: 577110016, available: 104857600
nvinfer: Tactic: 6 time 10.7429
nvinfer: Tactic: 57 time 9.10256
nvinfer: Fastest Tactic: 57 Time: 9.10256
nvinfer: --------------- Timing Runner: conv4_1 + relu4_1 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_1 + relu4_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328) -> Float(1,38,1444,739328) ***************
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv4_2 + relu4_2 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: conv4_2 + relu4_2 (CaskConvolution)
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 18.8248
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 19.4556
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 15.5808
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 14.7987
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 14.832
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 12.6366
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 15.3879
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 18.9066
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 15.1054
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 18.4954
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 19.6811
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 16.8068
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 19.2886
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 11.5467
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 14.4569
nvinfer: Fastest Tactic: -1343271414618805657 Time: 11.5467
nvinfer: --------------- Timing Runner: conv4_2 + relu4_2 (CudaConvolution)
nvinfer: Tactic: 0 time 34.6919
nvinfer: Tactic: 2 time 39.4678
nvinfer: Tactic: 5 skipped. Scratch requested: 1149763584, available: 104857600
nvinfer: Tactic: 6 time 12.5517
nvinfer: Tactic: 57 time 17.7433
nvinfer: Fastest Tactic: 6 Time: 12.5517
nvinfer: --------------- Timing Runner: conv4_2 + relu4_2 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_2 + relu4_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328) -> Float(1,38,1444,739328) ***************
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328) -> Float(1,38,1444,739328) ***************
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328), Float(1,300,90000,270000) -> Float(1,1,23104,46208) ***************
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328) -> Float(1,38,1444,144400) ***************
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 5.48534
nvinfer: Tactic: 720895 time 4.10496
nvinfer: Tactic: 983039 time 4.46656
nvinfer: Tactic: 1048575 time 4.70192
nvinfer: Tactic: 1703935 time 5.17594
nvinfer: Tactic: 1769471 time 4.90838
nvinfer: Tactic: 1966079 time 4.31846
nvinfer: Tactic: 2031615 time 4.05392
nvinfer: Tactic: 2228223 time 4.72016
nvinfer: Tactic: 2424831 time 5.62752
nvinfer: Tactic: 2621439 time 5.54634
nvinfer: Tactic: 2752511 time 4.41152
nvinfer: Tactic: 2818047 time 6.77072
nvinfer: Tactic: 2883583 time 4.44496
nvinfer: Tactic: 3014655 time 4.42406
nvinfer: Tactic: 3145727 time 4.54432
nvinfer: Tactic: 3473407 time 4.17626
nvinfer: Tactic: 3604479 time 4.35482
nvinfer: Tactic: 3735551 time 4.53635
nvinfer: Tactic: 4390911 time 4.20688
nvinfer: Tactic: 5046271 time 6.13824
nvinfer: Tactic: 5963775 time 4.1904
nvinfer: Tactic: 6160383 time 5.26915
nvinfer: Tactic: 6488063 time 4.64026
nvinfer: Tactic: 6881279 time 4.62992
nvinfer: Tactic: 7274495 time 5.7033
nvinfer: Tactic: 7864319 time 5.756
nvinfer: Tactic: 7995391 time 4.26784
nvinfer: Tactic: 8585215 time 4.49056
nvinfer: Tactic: 8847359 time 5.42656
nvinfer: Tactic: 8978431 time 4.30112
nvinfer: Tactic: 9043967 time 4.79824
nvinfer: Tactic: 9175039 time 4.45984
nvinfer: Tactic: 9502719 time 4.37408
nvinfer: Tactic: 9830399 time 4.41056
nvinfer: Tactic: 9961471 time 5.23072
nvinfer: Tactic: 10027007 time 4.69376
nvinfer: Tactic: 10092543 time 4.22096
nvinfer: Tactic: 10289151 time 4.29088
nvinfer: Tactic: 10485759 time 4.80688
nvinfer: Tactic: 10682367 time 5.29152
nvinfer: Tactic: 10813439 time 4.29904
nvinfer: Fastest Tactic: 2031615 Time: 4.05392
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (CaskConvolution)
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 4.70486
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 4.20118
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 3.9
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 3.66086
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 3.73792
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 3.19696
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 3.81728
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 4.35066
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 3.69872
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 4.16989
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 4.8904
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 4.1936
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 4.27437
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 2.6568
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 3.57456
nvinfer: Fastest Tactic: -1343271414618805657 Time: 2.6568
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 8.71094
nvinfer: Tactic: 2 time 9.91229
nvinfer: Tactic: 5 skipped. Scratch requested: 228149248, available: 104857600
nvinfer: Tactic: 6 time 4.75856
nvinfer: Tactic: 57 time 4.39958
nvinfer: Fastest Tactic: 57 Time: 4.39958
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.176
nvinfer: Tactic: 0 time 0.23904
nvinfer: Fastest Tactic: 1002 Time: 0.176
nvinfer: *************** Autotuning format combination: Float(1,38,1444,739328) -> Float(1,19,361,184832) ***************
nvinfer: --------------- Timing Runner: pool4 (Pooling)
nvinfer: Tactic: -1 time 0.172544
nvinfer: Fastest Tactic: -1 Time: 0.172544
nvinfer: --------------- Timing Runner: pool4 (TiledPooling)
nvinfer: Tactic: 5505281 time 0.431456
nvinfer: Tactic: 5570817 time 0.28112
nvinfer: Tactic: 5636353 time 0.210816
nvinfer: Tactic: 5701889 time 0.19088
nvinfer: Tactic: 5767425 time 0.18192
nvinfer: Tactic: 5832961 time 0.22224
nvinfer: Tactic: 5898497 time 0.17632
nvinfer: Tactic: 5964033 time 0.1832
nvinfer: Tactic: 6029569 time 0.495488
nvinfer: Tactic: 6095105 time 0.31584
nvinfer: Tactic: 6160641 time 0.270304
nvinfer: Tactic: 6226177 time 0.274016
nvinfer: Tactic: 6291713 time 0.28832
nvinfer: Tactic: 6357249 time 0.35504
nvinfer: Tactic: 6422785 time 0.2872
nvinfer: Tactic: 6488321 time 0.281696
nvinfer: Fastest Tactic: 5898497 Time: 0.17632
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: Pooling Tactic: -1
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,19,361,184832) -> Float(1,19,361,184832) ***************
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv5_1 + relu5_1 (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 5.76896
nvinfer: Tactic: 720895 time 5.31984
nvinfer: Tactic: 983039 time 5.08515
nvinfer: Tactic: 1048575 time 5.41584
nvinfer: Tactic: 1703935 time 5.42096
nvinfer: Tactic: 1769471 time 5.01242
nvinfer: Tactic: 1966079 time 5.32886
nvinfer: Tactic: 2031615 time 4.93418
nvinfer: Tactic: 2228223 time 6.6703
nvinfer: Tactic: 2424831 time 7.74125
nvinfer: Tactic: 2621439 time 6.83421
nvinfer: Tactic: 2752511 time 4.60112
nvinfer: Tactic: 2818047 time 7.29418
nvinfer: Tactic: 2883583 time 5.2896
nvinfer: Tactic: 3014655 time 5.61152
nvinfer: Tactic: 3145727 time 4.67853
nvinfer: Tactic: 3473407 time 5.15984
nvinfer: Tactic: 3604479 time 5.52365
nvinfer: Tactic: 3735551 time 6.1376
nvinfer: Tactic: 4390911 time 4.68736
nvinfer: Tactic: 5046271 time 5.73907
nvinfer: Tactic: 5963775 time 4.84256
nvinfer: Tactic: 6160383 time 5.21952
nvinfer: Tactic: 6488063 time 5.04256
nvinfer: Tactic: 6881279 time 6.01581
nvinfer: Tactic: 7274495 time 8.07459
nvinfer: Tactic: 7864319 time 6.92506
nvinfer: Tactic: 7995391 time 5.45898
nvinfer: Tactic: 8585215 time 4.91568
nvinfer: Tactic: 8847359 time 5.39136
nvinfer: Tactic: 8978431 time 4.88416
nvinfer: Tactic: 9043967 time 5.13792
nvinfer: Tactic: 9175039 time 5.36496
nvinfer: Tactic: 9502719 time 4.62224
nvinfer: Tactic: 9830399 time 7.83878
nvinfer: Tactic: 9961471 time 6.18054
nvinfer: Tactic: 10027007 time 5.14192
nvinfer: Tactic: 10092543 time 4.50608
nvinfer: Tactic: 10289151 time 5.04054
nvinfer: Tactic: 10485759 time 5.05632
nvinfer: Tactic: 10682367 time 6.5776
nvinfer: Tactic: 10813439 time 5.40886
nvinfer: Fastest Tactic: 10092543 Time: 4.50608
nvinfer: --------------- Timing Runner: conv5_1 + relu5_1 (CaskConvolution)
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 4.7831
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 6.54582
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 3.96006
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 3.83536
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 3.7311
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 4.68042
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 3.95382
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 6.9777
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 3.816
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 6.31606
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 4.9528
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 4.20576
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 6.81424
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 4.21536
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 3.62704
nvinfer: Fastest Tactic: -410470605513481746 Time: 3.62704
nvinfer: --------------- Timing Runner: conv5_1 + relu5_1 (CudaConvolution)
nvinfer: Tactic: 0 time 9.15334
nvinfer: Tactic: 2 time 9.10176
nvinfer: Tactic: 5 skipped. Scratch requested: 1145307136, available: 104857600
nvinfer: Tactic: 6 time 5.776
nvinfer: Tactic: 57 time 4.59248
nvinfer: Fastest Tactic: 57 Time: 4.59248
nvinfer: --------------- Timing Runner: conv5_1 + relu5_1 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -410470605513481746
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: 
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,19,361,184832) -> Float(1,19,361,184832) ***************
nvinfer: *************** Autotuning format combination: Float(1,19,361,184832) -> Float(1,19,361,184832) ***************
nvinfer: *************** Autotuning format combination: Float(1,19,361,184832) -> Float(1,19,361,184832) ***************
nvinfer: --------------- Timing Runner: pool5 (Pooling)
nvinfer: Tactic: -1 time 0.232896
nvinfer: Fastest Tactic: -1 Time: 0.232896
nvinfer: --------------- Timing Runner: pool5 (TiledPooling)
nvinfer: Tactic: 2752769 time 0.263392
nvinfer: Tactic: 2818305 time 0.29776
nvinfer: Tactic: 2883841 time 0.23744
nvinfer: Tactic: 2949377 time 0.4856
nvinfer: Tactic: 3014913 time 0.411424
nvinfer: Tactic: 3080449 time 0.2144
nvinfer: Tactic: 3145985 time 0.20768
nvinfer: Tactic: 3211521 time 0.305536
nvinfer: Tactic: 3277057 time 0.265696
nvinfer: Tactic: 3342593 time 0.17408
nvinfer: Tactic: 3408129 time 0.28544
nvinfer: Tactic: 3473665 time 0.23712
nvinfer: Tactic: 3539201 time 0.136
nvinfer: Tactic: 3604737 time 0.127264
nvinfer: Tactic: 3670273 time 0.2816
nvinfer: Tactic: 3735809 time 0.27088
nvinfer: Tactic: 3801345 time 0.21856
nvinfer: Tactic: 3866881 time 0.22944
nvinfer: Tactic: 3932417 time 0.183392
nvinfer: Tactic: 3997953 time 0.11408
nvinfer: Tactic: 4063489 time 0.11344
nvinfer: Tactic: 4129025 time 0.27184
nvinfer: Tactic: 4194561 time 0.26544
nvinfer: Tactic: 4260097 time 0.17488
nvinfer: Tactic: 4325633 time 0.20288
nvinfer: Tactic: 4391169 time 0.15712
nvinfer: Tactic: 4456705 time 0.09856
nvinfer: Tactic: 4522241 time 0.0976
nvinfer: Tactic: 4587777 time 0.333344
nvinfer: Tactic: 4653313 time 0.270336
nvinfer: Tactic: 4718849 time 0.170176
nvinfer: Tactic: 4784385 time 0.18752
nvinfer: Tactic: 4849921 time 0.15216
nvinfer: Tactic: 4915457 time 0.09488
nvinfer: Tactic: 4980993 time 0.093056
nvinfer: Tactic: 5046529 time 0.291584
nvinfer: Tactic: 5112065 time 0.283776
nvinfer: Tactic: 5177601 time 0.17312
nvinfer: Tactic: 5243137 time 0.17328
nvinfer: Tactic: 5308673 time 0.141024
nvinfer: Tactic: 5374209 time 0.091392
nvinfer: Tactic: 5439745 time 0.0896
nvinfer: Tactic: 6553857 time 0.082624
nvinfer: Tactic: 6750465 time 0.12768
nvinfer: Fastest Tactic: 6553857 Time: 0.082624
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: TiledPooling Tactic: 6553857
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,19,361,184832) -> Float(1,19,361,369664) ***************
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: --------------- Timing Runner: fc6 + relu6 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: fc6 + relu6 (CaskConvolution)
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 19.8865
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 12.3743
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 9.1001
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 12.4875
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 10.0802
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 19.9288
nvinfer: Fastest Tactic: 4501471010995462441 Time: 9.1001
nvinfer: --------------- Timing Runner: fc6 + relu6 (CudaConvolution)
nvinfer: Tactic: 0 time 19.3861
nvinfer: Tactic: 2 time 17.9667
nvinfer: Tactic: 57 time 19.3339
nvinfer: Fastest Tactic: 2 Time: 17.9667
nvinfer: --------------- Timing Runner: fc6 + relu6 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 4501471010995462441
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: 
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,19,361,369664) -> Float(1,19,361,369664) ***************
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: fc7 + relu7 (FusedConvActConvolution)
nvinfer: FusedConvActConvolution has no valid tactics for this config, skipping
nvinfer: --------------- Timing Runner: fc7 + relu7 (CaskConvolution)
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 2.12352
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 1.79722
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 1.7559
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 1.71296
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 1.76112
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 1.97414
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 2.05078
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 1.72688
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 1.69936
nvinfer: Fastest Tactic: -37215280111360163 Time: 1.69936
nvinfer: --------------- Timing Runner: fc7 + relu7 (CudaConvolution)
nvinfer: Tactic: 0 time 4.7856
nvinfer: Tactic: 2 time 4.37664
nvinfer: Tactic: 5 skipped. Scratch requested: 147898368, available: 104857600
nvinfer: Tactic: 57 time 3.68022
nvinfer: Fastest Tactic: 57 Time: 3.68022
nvinfer: --------------- Timing Runner: fc7 + relu7 (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -37215280111360163
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: 
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,19,361,369664), Float(1,300,90000,270000) -> Float(1,1,8664,17328) ***************
nvinfer: *************** Autotuning format combination: Float(1,19,361,369664) -> Float(1,19,361,54150) ***************
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: fc7_mbox_loc || fc7_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 4.20074
nvinfer: Tactic: 720895 time 3.64438
nvinfer: Tactic: 983039 time 3.64288
nvinfer: Tactic: 1048575 time 3.53674
nvinfer: Tactic: 1703935 time 3.58826
nvinfer: Tactic: 1769471 time 3.48502
nvinfer: Tactic: 1966079 time 3.93088
nvinfer: Tactic: 2031615 time 3.26794
nvinfer: Tactic: 2228223 time 4.09664
nvinfer: Tactic: 2424831 time 4.7609
nvinfer: Tactic: 2621439 time 3.956
nvinfer: Tactic: 2752511 time 3.60067
nvinfer: Tactic: 3014655 time 3.40912
nvinfer: Tactic: 3145727 time 3.28982
nvinfer: Tactic: 3604479 time 3.3896
nvinfer: Tactic: 4390911 time 4.15178
nvinfer: Tactic: 5046271 time 3.7241
nvinfer: Tactic: 5963775 time 3.47322
nvinfer: Tactic: 6160383 time 3.3608
nvinfer: Tactic: 6488063 time 3.1329
nvinfer: Tactic: 6881279 time 3.50899
nvinfer: Tactic: 7274495 time 4.77706
nvinfer: Tactic: 7864319 time 4.35248
nvinfer: Tactic: 7995391 time 3.92768
nvinfer: Tactic: 8585215 time 3.36224
nvinfer: Tactic: 8847359 time 3.42656
nvinfer: Tactic: 8978431 time 3.49866
nvinfer: Tactic: 9043967 time 3.0912
nvinfer: Tactic: 9175039 time 3.34464
nvinfer: Tactic: 9502719 time 4.18912
nvinfer: Tactic: 9961471 time 4.00544
nvinfer: Tactic: 10027007 time 2.84896
nvinfer: Tactic: 10092543 time 4.14432
nvinfer: Tactic: 10289151 time 3.8832
nvinfer: Tactic: 10485759 time 3.06272
nvinfer: Tactic: 10682367 time 4.12064
nvinfer: Tactic: 10813439 time 3.89248
nvinfer: Fastest Tactic: 10027007 Time: 2.84896
nvinfer: --------------- Timing Runner: fc7_mbox_loc || fc7_mbox_conf (CaskConvolution)
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 4.14304
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 3.95194
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 3.9847
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 4.02022
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 3.59184
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 2.85066
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 3.89482
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 3.9504
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 4.96115
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 3.75856
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 4.22506
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 3.39456
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 3.90842
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 2.692
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 4.71376
nvinfer: Fastest Tactic: -1343271414618805657 Time: 2.692
nvinfer: --------------- Timing Runner: fc7_mbox_loc || fc7_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 6.6848
nvinfer: Tactic: 2 time 6.1712
nvinfer: Tactic: 5 skipped. Scratch requested: 673576448, available: 104857600
nvinfer: Tactic: 6 time 3.32266
nvinfer: Tactic: 57 time 3.68122
nvinfer: Fastest Tactic: 6 Time: 3.32266
nvinfer: --------------- Timing Runner: fc7_mbox_loc || fc7_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.05312
nvinfer: Tactic: 0 time 0.056
nvinfer: Fastest Tactic: 1002 Time: 0.05312
nvinfer: *************** Autotuning format combination: Float(1,19,361,369664) -> Float(1,19,361,92416) ***************
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv6_1 + conv6_1_relu (FusedConvActConvolution)
nvinfer: Tactic: 589823 time 1.67725
nvinfer: Tactic: 655359 time 1.35536
nvinfer: Tactic: 786431 time 1.29952
nvinfer: Tactic: 851967 time 1.31776
nvinfer: Tactic: 1179647 time 1.71968
nvinfer: Tactic: 1310719 time 3.21366
nvinfer: Tactic: 1376255 time 1.43712
nvinfer: Tactic: 1441791 time 1.45344
nvinfer: Tactic: 1507327 time 1.2287
nvinfer: Tactic: 1638399 time 1.63789
nvinfer: Tactic: 1835007 time 1.252
nvinfer: Tactic: 1900543 time 1.38826
nvinfer: Tactic: 2097151 time 1.52442
nvinfer: Tactic: 2162687 time 1.092
nvinfer: Tactic: 2293759 time 1.38026
nvinfer: Tactic: 2359295 time 1.11232
nvinfer: Tactic: 2686975 time 1.00486
nvinfer: Tactic: 3080191 time 1.41962
nvinfer: Tactic: 3342335 time 1.47686
nvinfer: Tactic: 3407871 time 1.27482
nvinfer: Tactic: 3538943 time 1.2905
nvinfer: Tactic: 3670015 time 0.958304
nvinfer: Tactic: 3932159 time 1.29786
nvinfer: Tactic: 3997695 time 1.44186
nvinfer: Tactic: 4063231 time 1.4152
nvinfer: Tactic: 4194303 time 1.19082
nvinfer: Tactic: 4259839 time 1.54614
nvinfer: Tactic: 4325375 time 1.25632
nvinfer: Tactic: 4521983 time 1.16102
nvinfer: Tactic: 4587519 time 1.6039
nvinfer: Tactic: 4653055 time 1.7664
nvinfer: Tactic: 4915199 time 1.26806
nvinfer: Tactic: 4980735 time 1.25952
nvinfer: Tactic: 5177343 time 1.46672
nvinfer: Tactic: 5242879 time 1.08208
nvinfer: Tactic: 5373951 time 2.20992
nvinfer: Tactic: 5439487 time 1.79085
nvinfer: Tactic: 5570559 time 1.22986
nvinfer: Tactic: 5636095 time 1.40768
nvinfer: Tactic: 5701631 time 1.45344
nvinfer: Tactic: 5767167 time 3.2536
nvinfer: Tactic: 5832703 time 1.21878
nvinfer: Tactic: 5898239 time 1.0329
nvinfer: Tactic: 6029311 time 1.42432
nvinfer: Tactic: 6225919 time 1.12576
nvinfer: Tactic: 6291455 time 1.72064
nvinfer: Tactic: 6422527 time 1.1552
nvinfer: Tactic: 6750207 time 1.6297
nvinfer: Tactic: 6815743 time 1.21696
nvinfer: Tactic: 6946815 time 1.99856
nvinfer: Tactic: 7012351 time 1.54938
nvinfer: Tactic: 7077887 time 1.3552
nvinfer: Tactic: 7143423 time 2.16944
nvinfer: Tactic: 7208959 time 1.12912
nvinfer: Tactic: 7340031 time 1.07654
nvinfer: Tactic: 7405567 time 1.42656
nvinfer: Tactic: 7536639 time 1.66627
nvinfer: Tactic: 7602175 time 1.81302
nvinfer: Tactic: 7733247 time 1.25238
nvinfer: Tactic: 7798783 time 1.26736
nvinfer: Tactic: 8191999 time 2.10784
nvinfer: Tactic: 8257535 time 1.40848
nvinfer: Tactic: 8323071 time 1.3352
nvinfer: Tactic: 8650751 time 1.73504
nvinfer: Tactic: 8716287 time 1.49936
nvinfer: Tactic: 9109503 time 1.63904
nvinfer: Tactic: 9568255 time 1.2551
nvinfer: Tactic: 9895935 time 1.14736
nvinfer: Tactic: 10223615 time 1.02426
nvinfer: Tactic: 10354687 time 1.5936
nvinfer: Tactic: 10551295 time 1.40902
nvinfer: Tactic: 10747903 time 1.24582
nvinfer: Tactic: 10944511 time 1.22749
nvinfer: Fastest Tactic: 3670015 Time: 0.958304
nvinfer: --------------- Timing Runner: conv6_1 + conv6_1_relu (CaskConvolution)
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.54672
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.570016
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.47856
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.59968
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.51648
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.486464
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.50128
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.51296
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.47824
nvinfer: Fastest Tactic: -37215280111360163 Time: 0.47824
nvinfer: --------------- Timing Runner: conv6_1 + conv6_1_relu (CudaConvolution)
nvinfer: Tactic: 0 time 1.06928
nvinfer: Tactic: 2 time 1.32096
nvinfer: Tactic: 5 time 9.00138
nvinfer: Tactic: 57 time 1.0896
nvinfer: Fastest Tactic: 0 Time: 1.06928
nvinfer: --------------- Timing Runner: conv6_1 + conv6_1_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -37215280111360163
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: 
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,19,361,92416) -> Float(1,10,100,51200) ***************
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv6_2 + conv6_2_relu (FusedConvActConvolution)
nvinfer: Tactic: 458751 time 1.2728
nvinfer: Fastest Tactic: 458751 Time: 1.2728
nvinfer: --------------- Timing Runner: conv6_2 + conv6_2_relu (CaskConvolution)
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 1.15984
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.744
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.6792
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.64576
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.68752
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.6864
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 1.1887
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.9512
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.6552
nvinfer: Fastest Tactic: 5137655947464784826 Time: 0.64576
nvinfer: --------------- Timing Runner: conv6_2 + conv6_2_relu (CudaConvolution)
nvinfer: Tactic: 0 time 1.64528
nvinfer: Tactic: 2 time 1.388
nvinfer: Tactic: 5 skipped. Scratch requested: 573767680, available: 104857600
nvinfer: Tactic: 57 time 2.65494
nvinfer: Fastest Tactic: 2 Time: 1.388
nvinfer: --------------- Timing Runner: conv6_2 + conv6_2_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 5137655947464784826
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: 
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,10,100,51200), Float(1,300,90000,270000) -> Float(1,1,2400,4800) ***************
nvinfer: *************** Autotuning format combination: Float(1,10,100,51200) -> Float(1,10,100,15000) ***************
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc || conv6_2_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.657984
nvinfer: Tactic: 720895 time 0.477696
nvinfer: Tactic: 983039 time 0.75008
nvinfer: Tactic: 1048575 time 0.56112
nvinfer: Tactic: 1703935 time 0.56752
nvinfer: Tactic: 1769471 time 0.58912
nvinfer: Tactic: 1966079 time 1.00854
nvinfer: Tactic: 2031615 time 0.63424
nvinfer: Tactic: 2228223 time 1.02858
nvinfer: Tactic: 2424831 time 0.780864
nvinfer: Tactic: 2621439 time 0.68592
nvinfer: Tactic: 2752511 time 0.568256
nvinfer: Tactic: 3014655 time 0.763776
nvinfer: Tactic: 3145727 time 0.58608
nvinfer: Tactic: 3604479 time 0.764736
nvinfer: Tactic: 4390911 time 0.830016
nvinfer: Tactic: 5046271 time 0.704704
nvinfer: Tactic: 5963775 time 0.8848
nvinfer: Tactic: 6160383 time 0.65856
nvinfer: Tactic: 6488063 time 0.852576
nvinfer: Tactic: 6881279 time 0.686336
nvinfer: Tactic: 7274495 time 0.89072
nvinfer: Tactic: 7864319 time 0.671136
nvinfer: Tactic: 7995391 time 0.9624
nvinfer: Tactic: 8585215 time 0.653696
nvinfer: Tactic: 8847359 time 0.72896
nvinfer: Tactic: 8978431 time 0.91952
nvinfer: Tactic: 9043967 time 0.71056
nvinfer: Tactic: 9175039 time 0.786496
nvinfer: Tactic: 9502719 time 0.872416
nvinfer: Tactic: 9961471 time 0.86928
nvinfer: Tactic: 10027007 time 0.498656
nvinfer: Tactic: 10092543 time 0.831104
nvinfer: Tactic: 10289151 time 1.03514
nvinfer: Tactic: 10485759 time 0.51856
nvinfer: Tactic: 10682367 time 0.678144
nvinfer: Tactic: 10813439 time 0.838144
nvinfer: Fastest Tactic: 720895 Time: 0.477696
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc || conv6_2_mbox_conf (CaskConvolution)
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 1.0369
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.686976
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.89008
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.850656
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.74224
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.544224
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.848416
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.769664
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.89088
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.65872
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 1.08
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.839104
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.71264
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.453536
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.894528
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.453536
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc || conv6_2_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 1.056
nvinfer: Tactic: 2 time 1.0448
nvinfer: Tactic: 5 skipped. Scratch requested: 337114624, available: 104857600
nvinfer: Tactic: 6 time 1.04928
nvinfer: Tactic: 57 time 1.99642
nvinfer: Fastest Tactic: 2 Time: 1.0448
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc || conv6_2_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -1343271414618805657
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: 
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.02064
nvinfer: Tactic: 0 time 0.01872
nvinfer: Fastest Tactic: 0 Time: 0.01872
nvinfer: *************** Autotuning format combination: Float(1,10,100,51200) -> Float(1,10,100,12800) ***************
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv7_1 + conv7_1_relu (FusedConvActConvolution)
nvinfer: Tactic: 589823 time 0.21808
nvinfer: Tactic: 655359 time 0.151776
nvinfer: Tactic: 786431 time 0.078464
nvinfer: Tactic: 851967 time 0.082432
nvinfer: Tactic: 1179647 time 0.1
nvinfer: Tactic: 1310719 time 0.33776
nvinfer: Tactic: 1376255 time 0.156
nvinfer: Tactic: 1441791 time 0.085696
nvinfer: Tactic: 1507327 time 0.0888
nvinfer: Tactic: 1638399 time 0.094112
nvinfer: Tactic: 1835007 time 0.090528
nvinfer: Tactic: 1900543 time 0.156
nvinfer: Tactic: 2097151 time 0.1272
nvinfer: Tactic: 2162687 time 0.15776
nvinfer: Tactic: 2293759 time 0.15216
nvinfer: Tactic: 2359295 time 0.100832
nvinfer: Tactic: 2686975 time 0.1416
nvinfer: Tactic: 3080191 time 0.099904
nvinfer: Tactic: 3342335 time 0.0904
nvinfer: Tactic: 3407871 time 0.105536
nvinfer: Tactic: 3538943 time 0.09408
nvinfer: Tactic: 3670015 time 0.263424
nvinfer: Tactic: 3932159 time 0.12928
nvinfer: Tactic: 3997695 time 0.07984
nvinfer: Tactic: 4063231 time 0.088224
nvinfer: Tactic: 4194303 time 0.13456
nvinfer: Tactic: 4259839 time 0.14416
nvinfer: Tactic: 4325375 time 0.087616
nvinfer: Tactic: 4521983 time 0.148992
nvinfer: Tactic: 4587519 time 0.152256
nvinfer: Tactic: 4653055 time 0.117504
nvinfer: Tactic: 4915199 time 0.117344
nvinfer: Tactic: 4980735 time 0.10752
nvinfer: Tactic: 5177343 time 0.091424
nvinfer: Tactic: 5242879 time 0.098336
nvinfer: Tactic: 5373951 time 0.099424
nvinfer: Tactic: 5439487 time 0.129216
nvinfer: Tactic: 5570559 time 0.094016
nvinfer: Tactic: 5636095 time 0.0888
nvinfer: Tactic: 5701631 time 0.1504
nvinfer: Tactic: 5767167 time 0.167264
nvinfer: Tactic: 5832703 time 0.104736
nvinfer: Tactic: 5898239 time 0.08016
nvinfer: Tactic: 6029311 time 0.144704
nvinfer: Tactic: 6225919 time 0.08432
nvinfer: Tactic: 6291455 time 0.09376
nvinfer: Tactic: 6422527 time 0.0912
nvinfer: Tactic: 6750207 time 0.11024
nvinfer: Tactic: 6815743 time 0.10352
nvinfer: Tactic: 6946815 time 0.14624
nvinfer: Tactic: 7012351 time 0.126976
nvinfer: Tactic: 7077887 time 0.093056
nvinfer: Tactic: 7143423 time 0.174144
nvinfer: Tactic: 7208959 time 0.10432
nvinfer: Tactic: 7340031 time 0.08224
nvinfer: Tactic: 7405567 time 0.10016
nvinfer: Tactic: 7536639 time 0.136544
nvinfer: Tactic: 7602175 time 0.146816
nvinfer: Tactic: 7733247 time 0.094624
nvinfer: Tactic: 7798783 time 0.0808
nvinfer: Tactic: 8191999 time 0.150624
nvinfer: Tactic: 8257535 time 0.11648
nvinfer: Tactic: 8323071 time 0.13008
nvinfer: Tactic: 8650751 time 0.143424
nvinfer: Tactic: 8716287 time 0.089504
nvinfer: Tactic: 9109503 time 0.1256
nvinfer: Tactic: 9568255 time 0.11504
nvinfer: Tactic: 9895935 time 0.13344
nvinfer: Tactic: 10223615 time 0.154464
nvinfer: Tactic: 10354687 time 0.13872
nvinfer: Tactic: 10551295 time 0.112256
nvinfer: Tactic: 10747903 time 0.08944
nvinfer: Tactic: 10944511 time 0.10592
nvinfer: Fastest Tactic: 786431 Time: 0.078464
nvinfer: --------------- Timing Runner: conv7_1 + conv7_1_relu (CaskConvolution)
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.101184
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.087584
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.07344
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.09056
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.08144
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.078144
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.088384
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.08432
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.07456
nvinfer: Fastest Tactic: 5137655947464784826 Time: 0.07344
nvinfer: --------------- Timing Runner: conv7_1 + conv7_1_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.129504
nvinfer: Tactic: 2 time 0.282336
nvinfer: Tactic: 5 time 1.90208
nvinfer: Tactic: 57 time 0.105696
nvinfer: Fastest Tactic: 57 Time: 0.105696
nvinfer: --------------- Timing Runner: conv7_1 + conv7_1_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: 5137655947464784826
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: 
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,10,100,12800) -> Float(1,5,25,6400) ***************
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv7_2 + conv7_2_relu (FusedConvActConvolution)
nvinfer: Tactic: 458751 time 0.255104
nvinfer: Fastest Tactic: 458751 Time: 0.255104
nvinfer: --------------- Timing Runner: conv7_2 + conv7_2_relu (CaskConvolution)
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.272064
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.23008
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.20928
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.23792
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.235584
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.210304
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 0.28656
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.21808
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.20016
nvinfer: Fastest Tactic: -410470605513481746 Time: 0.20016
nvinfer: --------------- Timing Runner: conv7_2 + conv7_2_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.2528
nvinfer: Tactic: 2 time 0.26144
nvinfer: Tactic: 5 skipped. Scratch requested: 144277504, available: 104857600
nvinfer: Tactic: 57 time 0.33456
nvinfer: Fastest Tactic: 0 Time: 0.2528
nvinfer: --------------- Timing Runner: conv7_2 + conv7_2_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: CaskConvolution Tactic: -410470605513481746
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: 
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: *************** Autotuning format combination: Float(1,5,25,6400), Float(1,300,90000,270000) -> Float(1,1,600,1200) ***************
nvinfer: *************** Autotuning format combination: Float(1,5,25,6400) -> Float(1,5,25,3750) ***************
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc || conv7_2_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.26688
nvinfer: Tactic: 720895 time 0.17136
nvinfer: Tactic: 983039 time 0.121824
nvinfer: Tactic: 1048575 time 0.17888
nvinfer: Tactic: 1703935 time 0.108896
nvinfer: Tactic: 1769471 time 0.10656
nvinfer: Tactic: 1966079 time 0.3432
nvinfer: Tactic: 2031615 time 0.3184
nvinfer: Tactic: 2228223 time 0.26288
nvinfer: Tactic: 2424831 time 0.13312
nvinfer: Tactic: 2621439 time 0.113408
nvinfer: Tactic: 2752511 time 0.184416
nvinfer: Tactic: 3014655 time 0.13344
nvinfer: Tactic: 3145727 time 0.116224
nvinfer: Tactic: 3604479 time 0.12928
nvinfer: Tactic: 4390911 time 0.356704
nvinfer: Tactic: 5046271 time 0.15952
nvinfer: Tactic: 5963775 time 0.325024
nvinfer: Tactic: 6160383 time 0.22944
nvinfer: Tactic: 6488063 time 0.180064
nvinfer: Tactic: 6881279 time 0.28848
nvinfer: Tactic: 7274495 time 0.13952
nvinfer: Tactic: 7864319 time 0.12624
nvinfer: Tactic: 7995391 time 0.2048
nvinfer: Tactic: 8585215 time 0.2968
nvinfer: Tactic: 8847359 time 0.13712
nvinfer: Tactic: 8978431 time 0.34384
nvinfer: Tactic: 9043967 time 0.11856
nvinfer: Tactic: 9175039 time 0.13744
nvinfer: Tactic: 9502719 time 0.359616
nvinfer: Tactic: 9961471 time 0.15152
nvinfer: Tactic: 10027007 time 0.155104
nvinfer: Tactic: 10092543 time 0.36768
nvinfer: Tactic: 10289151 time 0.324384
nvinfer: Tactic: 10485759 time 0.100224
nvinfer: Tactic: 10682367 time 0.115424
nvinfer: Tactic: 10813439 time 0.143904
nvinfer: Fastest Tactic: 10485759 Time: 0.100224
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc || conv7_2_mbox_conf (CaskConvolution)
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.52576
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.19248
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.455136
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.418016
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.373696
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.16928
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.42512
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.1952
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.42976
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.18464
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 0.591136
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.443584
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.1848
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.14784
nvinfer: conv7_2_mbox_loc || conv7_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.38448
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.14784
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc || conv7_2_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 0.41872
nvinfer: Tactic: 2 time 0.41632
nvinfer: Tactic: 5 skipped. Scratch requested: 168883712, available: 104857600
nvinfer: Tactic: 6 time 0.396704
nvinfer: Tactic: 57 time 0.83024
nvinfer: Fastest Tactic: 6 Time: 0.396704
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc || conv7_2_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 10485759
nvinfer: 
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.010464
nvinfer: Tactic: 0 time 0.00816
nvinfer: Fastest Tactic: 0 Time: 0.00816
nvinfer: *************** Autotuning format combination: Float(1,5,25,6400) -> Float(1,5,25,3200) ***************
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv8_1 + conv8_1_relu (FusedConvActConvolution)
nvinfer: Tactic: 589823 time 0.07616
nvinfer: Tactic: 655359 time 0.049504
nvinfer: Tactic: 786431 time 0.02448
nvinfer: Tactic: 851967 time 0.02096
nvinfer: Tactic: 1179647 time 0.018176
nvinfer: Tactic: 1310719 time 0.09216
nvinfer: Tactic: 1376255 time 0.051776
nvinfer: Tactic: 1441791 time 0.01968
nvinfer: Tactic: 1507327 time 0.030976
nvinfer: Tactic: 1638399 time 0.024224
nvinfer: Tactic: 1835007 time 0.025056
nvinfer: Tactic: 1900543 time 0.055744
nvinfer: Tactic: 2097151 time 0.025184
nvinfer: Tactic: 2162687 time 0.05424
nvinfer: Tactic: 2293759 time 0.049056
nvinfer: Tactic: 2359295 time 0.036
nvinfer: Tactic: 2686975 time 0.049824
nvinfer: Tactic: 3080191 time 0.02896
nvinfer: Tactic: 3342335 time 0.03264
nvinfer: Tactic: 3407871 time 0.030496
nvinfer: Tactic: 3538943 time 0.021184
nvinfer: Tactic: 3670015 time 0.098208
nvinfer: Tactic: 3932159 time 0.044192
nvinfer: Tactic: 3997695 time 0.0152
nvinfer: Tactic: 4063231 time 0.020448
nvinfer: Tactic: 4194303 time 0.0272
nvinfer: Tactic: 4259839 time 0.027872
nvinfer: Tactic: 4325375 time 0.02576
nvinfer: Tactic: 4521983 time 0.05248
nvinfer: Tactic: 4587519 time 0.02224
nvinfer: Tactic: 4653055 time 0.01856
nvinfer: Tactic: 4915199 time 0.022688
nvinfer: Tactic: 4980735 time 0.04112
nvinfer: Tactic: 5177343 time 0.02368
nvinfer: Tactic: 5242879 time 0.029888
nvinfer: Tactic: 5373951 time 0.01776
nvinfer: Tactic: 5439487 time 0.02544
nvinfer: Tactic: 5570559 time 0.032128
nvinfer: Tactic: 5636095 time 0.02048
nvinfer: Tactic: 5701631 time 0.049696
nvinfer: Tactic: 5767167 time 0.02992
nvinfer: Tactic: 5832703 time 0.030176
nvinfer: Tactic: 5898239 time 0.018816
nvinfer: Tactic: 6029311 time 0.046656
nvinfer: Tactic: 6225919 time 0.019296
nvinfer: Tactic: 6291455 time 0.01792
nvinfer: Tactic: 6422527 time 0.027776
nvinfer: Tactic: 6750207 time 0.020704
nvinfer: Tactic: 6815743 time 0.0288
nvinfer: Tactic: 6946815 time 0.031296
nvinfer: Tactic: 7012351 time 0.02528
nvinfer: Tactic: 7077887 time 0.0208
nvinfer: Tactic: 7143423 time 0.02896
nvinfer: Tactic: 7208959 time 0.031136
nvinfer: Tactic: 7340031 time 0.01968
nvinfer: Tactic: 7405567 time 0.02208
nvinfer: Tactic: 7536639 time 0.04
nvinfer: Tactic: 7602175 time 0.03136
nvinfer: Tactic: 7733247 time 0.02128
nvinfer: Tactic: 7798783 time 0.02448
nvinfer: Tactic: 8191999 time 0.024
nvinfer: Tactic: 8257535 time 0.022272
nvinfer: Tactic: 8323071 time 0.0256
nvinfer: Tactic: 8650751 time 0.03296
nvinfer: Tactic: 8716287 time 0.020128
nvinfer: Tactic: 9109503 time 0.0248
nvinfer: Tactic: 9568255 time 0.02208
nvinfer: Tactic: 9895935 time 0.02752
nvinfer: Tactic: 10223615 time 0.04896
nvinfer: Tactic: 10354687 time 0.03008
nvinfer: Tactic: 10551295 time 0.031616
nvinfer: Tactic: 10747903 time 0.021056
nvinfer: Tactic: 10944511 time 0.041056
nvinfer: Fastest Tactic: 3997695 Time: 0.0152
nvinfer: --------------- Timing Runner: conv8_1 + conv8_1_relu (CaskConvolution)
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.0432
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.046304
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.033824
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.044896
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.036096
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.035904
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.036544
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.044544
nvinfer: conv8_1 + conv8_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.0328
nvinfer: Fastest Tactic: -37215280111360163 Time: 0.0328
nvinfer: --------------- Timing Runner: conv8_1 + conv8_1_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.0496
nvinfer: Tactic: 2 time 0.135904
nvinfer: Tactic: 5 time 1.11194
nvinfer: Tactic: 57 time 0.07408
nvinfer: Fastest Tactic: 0 Time: 0.0496
nvinfer: --------------- Timing Runner: conv8_1 + conv8_1_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 3997695
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,5,25,3200) -> Float(1,3,9,2304) ***************
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv8_2 + conv8_2_relu (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.13424
nvinfer: Tactic: 720895 time 0.091904
nvinfer: Tactic: 983039 time 0.06336
nvinfer: Tactic: 1048575 time 0.103776
nvinfer: Tactic: 1703935 time 0.086048
nvinfer: Tactic: 1769471 time 0.06112
nvinfer: Tactic: 1966079 time 0.16032
nvinfer: Tactic: 2031615 time 0.1744
nvinfer: Tactic: 2228223 time 0.133088
nvinfer: Tactic: 2424831 time 0.090752
nvinfer: Tactic: 2621439 time 0.07376
nvinfer: Tactic: 2752511 time 0.102944
nvinfer: Tactic: 2818047 time 0.16992
nvinfer: Tactic: 2883583 time 0.226496
nvinfer: Tactic: 3014655 time 0.088224
nvinfer: Tactic: 3145727 time 0.068992
nvinfer: Tactic: 3473407 time 0.12768
nvinfer: Tactic: 3604479 time 0.089984
nvinfer: Tactic: 3735551 time 0.124864
nvinfer: Tactic: 4390911 time 0.1952
nvinfer: Tactic: 5046271 time 0.084192
nvinfer: Tactic: 5963775 time 0.17136
nvinfer: Tactic: 6160383 time 0.12256
nvinfer: Tactic: 6488063 time 0.103584
nvinfer: Tactic: 6881279 time 0.164928
nvinfer: Tactic: 7274495 time 0.060032
nvinfer: Tactic: 7864319 time 0.0792
nvinfer: Tactic: 7995391 time 0.102016
nvinfer: Tactic: 8585215 time 0.167904
nvinfer: Tactic: 8847359 time 0.084384
nvinfer: Tactic: 8978431 time 0.17376
nvinfer: Tactic: 9043967 time 0.085376
nvinfer: Tactic: 9175039 time 0.09072
nvinfer: Tactic: 9502719 time 0.19088
nvinfer: Tactic: 9830399 time 0.086976
nvinfer: Tactic: 9961471 time 0.102816
nvinfer: Tactic: 10027007 time 0.09104
nvinfer: Tactic: 10092543 time 0.184
nvinfer: Tactic: 10289151 time 0.16352
nvinfer: Tactic: 10485759 time 0.06736
nvinfer: Tactic: 10682367 time 0.077376
nvinfer: Tactic: 10813439 time 0.066496
nvinfer: Fastest Tactic: 7274495 Time: 0.060032
nvinfer: --------------- Timing Runner: conv8_2 + conv8_2_relu (CaskConvolution)
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.249856
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.14768
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.24736
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.22192
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.199424
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.20736
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.13056
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.21568
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.14768
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.23136
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.13376
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.22704
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 0.27056
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.2448
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.13776
nvinfer: conv8_2 + conv8_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.09552
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.221856
nvinfer: conv8_2 + conv8_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.198816
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.09552
nvinfer: --------------- Timing Runner: conv8_2 + conv8_2_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.231776
nvinfer: Tactic: 2 time 0.237184
nvinfer: Tactic: 5 skipped. Scratch requested: 144277504, available: 104857600
nvinfer: Tactic: 6 time 0.32848
nvinfer: Tactic: 57 time 0.14608
nvinfer: Fastest Tactic: 57 Time: 0.14608
nvinfer: --------------- Timing Runner: conv8_2 + conv8_2_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 7274495
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,3,9,2304), Float(1,300,90000,270000) -> Float(1,1,144,288) ***************
nvinfer: *************** Autotuning format combination: Float(1,3,9,2304) -> Float(1,3,9,900) ***************
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc || conv8_2_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.26208
nvinfer: Tactic: 720895 time 0.16048
nvinfer: Tactic: 983039 time 0.090624
nvinfer: Tactic: 1048575 time 0.17024
nvinfer: Tactic: 1703935 time 0.09312
nvinfer: Tactic: 1769471 time 0.070656
nvinfer: Tactic: 1966079 time 0.30848
nvinfer: Tactic: 2031615 time 0.304704
nvinfer: Tactic: 2228223 time 0.261216
nvinfer: Tactic: 2424831 time 0.08832
nvinfer: Tactic: 2621439 time 0.06832
nvinfer: Tactic: 2752511 time 0.188544
nvinfer: Tactic: 2818047 time 0.31088
nvinfer: Tactic: 2883583 time 0.45584
nvinfer: Tactic: 3014655 time 0.107936
nvinfer: Tactic: 3145727 time 0.09552
nvinfer: Tactic: 3473407 time 0.23776
nvinfer: Tactic: 3604479 time 0.10256
nvinfer: Tactic: 3735551 time 0.21184
nvinfer: Tactic: 4390911 time 0.36288
nvinfer: Tactic: 5046271 time 0.13888
nvinfer: Tactic: 5963775 time 0.320544
nvinfer: Tactic: 6160383 time 0.22624
nvinfer: Tactic: 6488063 time 0.17184
nvinfer: Tactic: 6881279 time 0.281056
nvinfer: Tactic: 7274495 time 0.079104
nvinfer: Tactic: 7864319 time 0.0704
nvinfer: Tactic: 7995391 time 0.174816
nvinfer: Tactic: 8585215 time 0.299744
nvinfer: Tactic: 8847359 time 0.07824
nvinfer: Tactic: 8978431 time 0.338496
nvinfer: Tactic: 9043967 time 0.09696
nvinfer: Tactic: 9175039 time 0.11056
nvinfer: Tactic: 9502719 time 0.36048
nvinfer: Tactic: 9830399 time 0.15088
nvinfer: Tactic: 9961471 time 0.084896
nvinfer: Tactic: 10027007 time 0.15168
nvinfer: Tactic: 10092543 time 0.374016
nvinfer: Tactic: 10289151 time 0.309184
nvinfer: Tactic: 10485759 time 0.082624
nvinfer: Tactic: 10682367 time 0.068416
nvinfer: Tactic: 10813439 time 0.091616
nvinfer: Fastest Tactic: 2621439 Time: 0.06832
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc || conv8_2_mbox_conf (CaskConvolution)
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.47312
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.13376
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.399424
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.3832
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.31792
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.10832
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.395296
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.13488
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.422304
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.13264
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 0.493184
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.32784
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.13616
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.09888
nvinfer: conv8_2_mbox_loc || conv8_2_mbox_conf (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.36208
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.09888
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc || conv8_2_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 0.41264
nvinfer: Tactic: 2 time 0.36256
nvinfer: Tactic: 5 skipped. Scratch requested: 112960512, available: 104857600
nvinfer: Tactic: 6 time 0.31408
nvinfer: Tactic: 57 time 0.380864
nvinfer: Fastest Tactic: 6 Time: 0.31408
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc || conv8_2_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 2621439
nvinfer: 
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00896
nvinfer: Tactic: 0 time 0.0048
nvinfer: Fastest Tactic: 0 Time: 0.0048
nvinfer: *************** Autotuning format combination: Float(1,3,9,2304) -> Float(1,3,9,1152) ***************
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv9_1 + conv9_1_relu (FusedConvActConvolution)
nvinfer: Tactic: 589823 time 0.0744
nvinfer: Tactic: 655359 time 0.05024
nvinfer: Tactic: 786431 time 0.02368
nvinfer: Tactic: 851967 time 0.0184
nvinfer: Tactic: 1179647 time 0.012576
nvinfer: Tactic: 1310719 time 0.089376
nvinfer: Tactic: 1376255 time 0.05152
nvinfer: Tactic: 1441791 time 0.014464
nvinfer: Tactic: 1507327 time 0.029984
nvinfer: Tactic: 1638399 time 0.01536
nvinfer: Tactic: 1835007 time 0.022496
nvinfer: Tactic: 1900543 time 0.055616
nvinfer: Tactic: 2097151 time 0.01344
nvinfer: Tactic: 2162687 time 0.05328
nvinfer: Tactic: 2293759 time 0.05072
nvinfer: Tactic: 2359295 time 0.034464
nvinfer: Tactic: 2686975 time 0.051104
nvinfer: Tactic: 3080191 time 0.0272
nvinfer: Tactic: 3342335 time 0.0304
nvinfer: Tactic: 3407871 time 0.02816
nvinfer: Tactic: 3538943 time 0.01728
nvinfer: Tactic: 3670015 time 0.09632
nvinfer: Tactic: 3932159 time 0.041984
nvinfer: Tactic: 3997695 time 0.015424
nvinfer: Tactic: 4063231 time 0.01888
nvinfer: Tactic: 4194303 time 0.02384
nvinfer: Tactic: 4259839 time 0.01504
nvinfer: Tactic: 4325375 time 0.022304
nvinfer: Tactic: 4521983 time 0.052096
nvinfer: Tactic: 4587519 time 0.01552
nvinfer: Tactic: 4653055 time 0.01328
nvinfer: Tactic: 4915199 time 0.015296
nvinfer: Tactic: 4980735 time 0.031744
nvinfer: Tactic: 5177343 time 0.011776
nvinfer: Tactic: 5242879 time 0.025664
nvinfer: Tactic: 5373951 time 0.013344
nvinfer: Tactic: 5439487 time 0.022944
nvinfer: Tactic: 5570559 time 0.02864
nvinfer: Tactic: 5636095 time 0.019136
nvinfer: Tactic: 5701631 time 0.045536
nvinfer: Tactic: 5767167 time 0.0264
nvinfer: Tactic: 5832703 time 0.02736
nvinfer: Tactic: 5898239 time 0.01584
nvinfer: Tactic: 6029311 time 0.04768
nvinfer: Tactic: 6225919 time 0.01728
nvinfer: Tactic: 6291455 time 0.01248
nvinfer: Tactic: 6422527 time 0.024576
nvinfer: Tactic: 6750207 time 0.015904
nvinfer: Tactic: 6815743 time 0.02672
nvinfer: Tactic: 6946815 time 0.02928
nvinfer: Tactic: 7012351 time 0.0136
nvinfer: Tactic: 7077887 time 0.018304
nvinfer: Tactic: 7143423 time 0.02592
nvinfer: Tactic: 7208959 time 0.02688
nvinfer: Tactic: 7340031 time 0.014464
nvinfer: Tactic: 7405567 time 0.01552
nvinfer: Tactic: 7536639 time 0.038656
nvinfer: Tactic: 7602175 time 0.029984
nvinfer: Tactic: 7733247 time 0.0184
nvinfer: Tactic: 7798783 time 0.023744
nvinfer: Tactic: 8191999 time 0.019616
nvinfer: Tactic: 8257535 time 0.01584
nvinfer: Tactic: 8323071 time 0.02368
nvinfer: Tactic: 8650751 time 0.02784
nvinfer: Tactic: 8716287 time 0.0168
nvinfer: Tactic: 9109503 time 0.013824
nvinfer: Tactic: 9568255 time 0.016
nvinfer: Tactic: 9895935 time 0.02384
nvinfer: Tactic: 10223615 time 0.05008
nvinfer: Tactic: 10354687 time 0.014496
nvinfer: Tactic: 10551295 time 0.029536
nvinfer: Tactic: 10747903 time 0.018464
nvinfer: Tactic: 10944511 time 0.032096
nvinfer: Fastest Tactic: 5177343 Time: 0.011776
nvinfer: --------------- Timing Runner: conv9_1 + conv9_1_relu (CaskConvolution)
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.0432
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.046016
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.033536
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.04512
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.036
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.03472
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.036416
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.04432
nvinfer: conv9_1 + conv9_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.03264
nvinfer: Fastest Tactic: -37215280111360163 Time: 0.03264
nvinfer: --------------- Timing Runner: conv9_1 + conv9_1_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.04864
nvinfer: Tactic: 2 time 0.1352
nvinfer: Tactic: 5 time 0.933056
nvinfer: Tactic: 57 time 0.04128
nvinfer: Fastest Tactic: 57 Time: 0.04128
nvinfer: --------------- Timing Runner: conv9_1 + conv9_1_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 5177343
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,3,9,1152) -> Float(1,1,1,256) ***************
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: --------------- Timing Runner: conv9_2 + conv9_2_relu (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.140224
nvinfer: Tactic: 720895 time 0.088
nvinfer: Tactic: 983039 time 0.0632
nvinfer: Tactic: 1048575 time 0.098944
nvinfer: Tactic: 1703935 time 0.07248
nvinfer: Tactic: 1769471 time 0.058144
nvinfer: Tactic: 1966079 time 0.1656
nvinfer: Tactic: 2031615 time 0.15696
nvinfer: Tactic: 2228223 time 0.13168
nvinfer: Tactic: 2424831 time 0.08848
nvinfer: Tactic: 2621439 time 0.089536
nvinfer: Tactic: 2752511 time 0.10064
nvinfer: Tactic: 2818047 time 0.166976
nvinfer: Tactic: 2883583 time 0.22864
nvinfer: Tactic: 3014655 time 0.09936
nvinfer: Tactic: 3145727 time 0.069216
nvinfer: Tactic: 3473407 time 0.132256
nvinfer: Tactic: 3604479 time 0.08864
nvinfer: Tactic: 3735551 time 0.112576
nvinfer: Tactic: 4390911 time 0.18544
nvinfer: Tactic: 5046271 time 0.085696
nvinfer: Tactic: 5963775 time 0.162816
nvinfer: Tactic: 6160383 time 0.122656
nvinfer: Tactic: 6488063 time 0.102016
nvinfer: Tactic: 6881279 time 0.14464
nvinfer: Tactic: 7274495 time 0.0528
nvinfer: Tactic: 7864319 time 0.08112
nvinfer: Tactic: 7995391 time 0.098016
nvinfer: Tactic: 8585215 time 0.15792
nvinfer: Tactic: 8847359 time 0.093376
nvinfer: Tactic: 8978431 time 0.17728
nvinfer: Tactic: 9043967 time 0.080576
nvinfer: Tactic: 9175039 time 0.090496
nvinfer: Tactic: 9502719 time 0.1912
nvinfer: Tactic: 9830399 time 0.0864
nvinfer: Tactic: 9961471 time 0.09504
nvinfer: Tactic: 10027007 time 0.09856
nvinfer: Tactic: 10092543 time 0.183456
nvinfer: Tactic: 10289151 time 0.16208
nvinfer: Tactic: 10485759 time 0.06864
nvinfer: Tactic: 10682367 time 0.076416
nvinfer: Tactic: 10813439 time 0.080416
nvinfer: Fastest Tactic: 7274495 Time: 0.0528
nvinfer: --------------- Timing Runner: conv9_2 + conv9_2_relu (CaskConvolution)
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_medium_nn_v1
nvinfer: Tactic: 1062367460111450758 time 0.23808
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.14672
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_large_nn_v1
nvinfer: Tactic: 4337000649858996379 time 0.212416
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Tactic: 4501471010995462441 time 0.215296
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Tactic: 5137655947464784826 time 0.197696
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_interior_nn_v1
nvinfer: Tactic: 5326823351883942011 time 0.218944
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.106176
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_medium_nn_v1
nvinfer: Tactic: 6645123197870846056 time 0.20832
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.15136
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_large_nn_v1
nvinfer: Tactic: -9137461792520977713 time 0.21232
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.140704
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_interior_nn_v1
nvinfer: Tactic: -6576203419454146580 time 0.219456
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_large_nn_v1
nvinfer: Tactic: -6092040395344634144 time 0.26512
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x32_relu_small_nn_v1
nvinfer: Tactic: -3456450830548107839 time 0.221664
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.14432
nvinfer: conv9_2 + conv9_2_relu (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.096224
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Tactic: -410470605513481746 time 0.23984
nvinfer: conv9_2 + conv9_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Tactic: -37215280111360163 time 0.194944
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.096224
nvinfer: --------------- Timing Runner: conv9_2 + conv9_2_relu (CudaConvolution)
nvinfer: Tactic: 0 time 0.23312
nvinfer: Tactic: 2 time 0.228544
nvinfer: Tactic: 5 skipped. Scratch requested: 144277504, available: 104857600
nvinfer: Tactic: 6 time 0.40576
nvinfer: Tactic: 57 time 0.140416
nvinfer: Fastest Tactic: 57 Time: 0.140416
nvinfer: --------------- Timing Runner: conv9_2 + conv9_2_relu (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 7274495
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,1,1,256), Float(1,300,90000,270000) -> Float(1,1,16,32) ***************
nvinfer: *************** Autotuning format combination: Float(1,1,1,256) -> Float(1,1,1,100) ***************
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc || conv9_2_mbox_conf (FusedConvActConvolution)
nvinfer: Tactic: 524287 time 0.270016
nvinfer: Tactic: 720895 time 0.159904
nvinfer: Tactic: 983039 time 0.0888
nvinfer: Tactic: 1048575 time 0.16832
nvinfer: Tactic: 1703935 time 0.0944
nvinfer: Tactic: 1769471 time 0.0728
nvinfer: Tactic: 1966079 time 0.306944
nvinfer: Tactic: 2031615 time 0.303104
nvinfer: Tactic: 2228223 time 0.26208
nvinfer: Tactic: 2424831 time 0.07904
nvinfer: Tactic: 2621439 time 0.069216
nvinfer: Tactic: 2752511 time 0.192864
nvinfer: Tactic: 2818047 time 0.314816
nvinfer: Tactic: 2883583 time 0.43472
nvinfer: Tactic: 3014655 time 0.11152
nvinfer: Tactic: 3145727 time 0.097536
nvinfer: Tactic: 3473407 time 0.23552
nvinfer: Tactic: 3604479 time 0.10368
nvinfer: Tactic: 3735551 time 0.23648
nvinfer: Tactic: 4390911 time 0.361216
nvinfer: Tactic: 5046271 time 0.1408
nvinfer: Tactic: 5963775 time 0.337696
nvinfer: Tactic: 6160383 time 0.246176
nvinfer: Tactic: 6488063 time 0.17056
nvinfer: Tactic: 6881279 time 0.281856
nvinfer: Tactic: 7274495 time 0.0672
nvinfer: Tactic: 7864319 time 0.071424
nvinfer: Tactic: 7995391 time 0.16944
nvinfer: Tactic: 8585215 time 0.293696
nvinfer: Tactic: 8847359 time 0.082816
nvinfer: Tactic: 8978431 time 0.33216
nvinfer: Tactic: 9043967 time 0.098304
nvinfer: Tactic: 9175039 time 0.1008
nvinfer: Tactic: 9502719 time 0.36112
nvinfer: Tactic: 9830399 time 0.15232
nvinfer: Tactic: 9961471 time 0.086464
nvinfer: Tactic: 10027007 time 0.14608
nvinfer: Tactic: 10092543 time 0.35536
nvinfer: Tactic: 10289151 time 0.3128
nvinfer: Tactic: 10485759 time 0.098464
nvinfer: Tactic: 10682367 time 0.07344
nvinfer: Tactic: 10813439 time 0.092224
nvinfer: Fastest Tactic: 7274495 Time: 0.0672
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc || conv9_2_mbox_conf (CaskConvolution)
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v1
nvinfer: Tactic: 3827454225649558724 time 0.133184
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Tactic: 5921334924264294896 time 0.09984
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v1
nvinfer: Tactic: 7852627285308570038 time 0.139584
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148n_nt_v0
nvinfer: Tactic: -8776506421218919509 time 0.12368
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148t_nt_v0
nvinfer: Tactic: -2318106587342035239 time 0.12592
nvinfer: conv9_2_mbox_loc || conv9_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Tactic: -1343271414618805657 time 0.08992
nvinfer: Fastest Tactic: -1343271414618805657 Time: 0.08992
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc || conv9_2_mbox_conf (CudaConvolution)
nvinfer: Tactic: 0 time 0.360576
nvinfer: Tactic: 2 time 0.30992
nvinfer: Tactic: 5 skipped. Scratch requested: 112960512, available: 104857600
nvinfer: Tactic: 6 time 0.28736
nvinfer: Tactic: 57 time 0.362464
nvinfer: Fastest Tactic: 6 Time: 0.28736
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc || conv9_2_mbox_conf (CudaDepthwiseConvolution)
nvinfer: CudaDepthwiseConvolution has no valid tactics for this config, skipping
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: FusedConvActConvolution Tactic: 7274495
nvinfer: 
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.007296
nvinfer: Tactic: 0 time 0.00304
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.04048
nvinfer: Tactic: 0 time 0.02688
nvinfer: Fastest Tactic: 0 Time: 0.02688
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.036096
nvinfer: Tactic: 0 time 0.018624
nvinfer: Fastest Tactic: 0 Time: 0.018624
nvinfer: *************** Autotuning format combination: Float(1,38,1444,144400) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.016224
nvinfer: Tactic: 1 time 0.032064
nvinfer: Fastest Tactic: 0 Time: 0.016224
nvinfer: *************** Autotuning format combination: Float(1,38,1444:32,5776) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.02128
nvinfer: Tactic: 1 time 0.07168
nvinfer: Fastest Tactic: 0 Time: 0.02128
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.03264
nvinfer: Tactic: 0 time 0.01696
nvinfer: Fastest Tactic: 0 Time: 0.01696
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.034304
nvinfer: Tactic: 0 time 0.01696
nvinfer: Fastest Tactic: 0 Time: 0.01696
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.01568
nvinfer: Tactic: 0 time 0.012576
nvinfer: Fastest Tactic: 0 Time: 0.012576
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.021504
nvinfer: Tactic: 0 time 0.00848
nvinfer: Fastest Tactic: 0 Time: 0.00848
nvinfer: *************** Autotuning format combination: Float(1,19,361,54150) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: fc7_mbox_loc_perm + fc7_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.007296
nvinfer: Tactic: 1 time 0.01536
nvinfer: Fastest Tactic: 0 Time: 0.007296
nvinfer: *************** Autotuning format combination: Float(1,19,361:32,1805) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: fc7_mbox_loc_perm + fc7_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00928
nvinfer: Tactic: 1 time 0.030464
nvinfer: Fastest Tactic: 0 Time: 0.00928
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.01536
nvinfer: Tactic: 0 time 0.008064
nvinfer: Fastest Tactic: 0 Time: 0.008064
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.015104
nvinfer: Tactic: 0 time 0.010464
nvinfer: Fastest Tactic: 0 Time: 0.010464
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.0072
nvinfer: Tactic: 0 time 0.00608
nvinfer: Fastest Tactic: 0 Time: 0.00608
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.013056
nvinfer: Tactic: 0 time 0.005344
nvinfer: Fastest Tactic: 0 Time: 0.005344
nvinfer: *************** Autotuning format combination: Float(1,10,100,15000) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.005056
nvinfer: Tactic: 1 time 0.009344
nvinfer: Fastest Tactic: 0 Time: 0.005056
nvinfer: *************** Autotuning format combination: Float(1,10,100:32,500) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.004864
nvinfer: Tactic: 1 time 0.015616
nvinfer: Fastest Tactic: 0 Time: 0.004864
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.008864
nvinfer: Tactic: 0 time 0.005184
nvinfer: Fastest Tactic: 0 Time: 0.005184
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00864
nvinfer: Tactic: 0 time 0.00544
nvinfer: Fastest Tactic: 0 Time: 0.00544
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.009024
nvinfer: Tactic: 0 time 0.0048
nvinfer: Fastest Tactic: 0 Time: 0.0048
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.007904
nvinfer: Tactic: 0 time 0.004864
nvinfer: Fastest Tactic: 0 Time: 0.004864
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.010496
nvinfer: Tactic: 0 time 0.003616
nvinfer: Fastest Tactic: 0 Time: 0.003616
nvinfer: *************** Autotuning format combination: Float(1,5,25,3750) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.003296
nvinfer: Tactic: 1 time 0.0088
nvinfer: Fastest Tactic: 0 Time: 0.003296
nvinfer: *************** Autotuning format combination: Float(1,5,25:32,125) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00352
nvinfer: Tactic: 1 time 0.01504
nvinfer: Fastest Tactic: 0 Time: 0.00352
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00816
nvinfer: Tactic: 0 time 0.003264
nvinfer: Fastest Tactic: 0 Time: 0.003264
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00896
nvinfer: Tactic: 0 time 0.00352
nvinfer: Fastest Tactic: 0 Time: 0.00352
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.008544
nvinfer: Tactic: 0 time 0.003296
nvinfer: Fastest Tactic: 0 Time: 0.003296
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00528
nvinfer: Tactic: 0 time 0.0032
nvinfer: Fastest Tactic: 0 Time: 0.0032
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.006496
nvinfer: Tactic: 0 time 0.003104
nvinfer: Fastest Tactic: 0 Time: 0.003104
nvinfer: *************** Autotuning format combination: Float(1,3,9,900) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00336
nvinfer: Tactic: 1 time 0.00768
nvinfer: Fastest Tactic: 0 Time: 0.00336
nvinfer: *************** Autotuning format combination: Float(1,3,9:32,36) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.003584
nvinfer: Tactic: 1 time 0.01264
nvinfer: Fastest Tactic: 0 Time: 0.003584
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00816
nvinfer: Tactic: 0 time 0.00304
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.007456
nvinfer: Tactic: 0 time 0.002976
nvinfer: Fastest Tactic: 0 Time: 0.002976
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.010624
nvinfer: Tactic: 0 time 0.003104
nvinfer: Fastest Tactic: 0 Time: 0.003104
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.006464
nvinfer: Tactic: 0 time 0.00304
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00736
nvinfer: Tactic: 0 time 0.003136
nvinfer: Fastest Tactic: 0 Time: 0.003136
nvinfer: *************** Autotuning format combination: Float(1,1,1,100) -> Float(1,1,1,34928) ***************
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00304
nvinfer: Tactic: 1 time 0.009504
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: *************** Autotuning format combination: Float(1,1,1:32,4) -> Float(1,1,1:32,1092) ***************
nvinfer: --------------- Timing Runner: conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat (Shuffle)
nvinfer: Tactic: 0 time 0.003104
nvinfer: Tactic: 1 time 0.05968
nvinfer: Fastest Tactic: 0 Time: 0.003104
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.0064
nvinfer: Tactic: 0 time 0.00352
nvinfer: Fastest Tactic: 0 Time: 0.00352
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.0064
nvinfer: Tactic: 0 time 0.00304
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.021056
nvinfer: Tactic: 0 time 0.02864
nvinfer: Fastest Tactic: 1002 Time: 0.021056
nvinfer: --------------- Timing Runner: fc7_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.01024
nvinfer: Tactic: 0 time 0.01232
nvinfer: Fastest Tactic: 1002 Time: 0.01024
nvinfer: --------------- Timing Runner: conv6_2_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.005216
nvinfer: Tactic: 0 time 0.0064
nvinfer: Fastest Tactic: 1002 Time: 0.005216
nvinfer: --------------- Timing Runner: conv7_2_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.005024
nvinfer: Tactic: 0 time 0.00336
nvinfer: Fastest Tactic: 0 Time: 0.00336
nvinfer: --------------- Timing Runner: conv8_2_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.00496
nvinfer: Tactic: 0 time 0.003104
nvinfer: Fastest Tactic: 0 Time: 0.003104
nvinfer: --------------- Timing Runner: conv9_2_mbox_priorbox copy (Reformat)
nvinfer: Tactic: 1002 time 0.004896
nvinfer: Tactic: 0 time 0.002944
nvinfer: Fastest Tactic: 0 Time: 0.002944
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.127296
nvinfer: Tactic: 0 time 0.16992
nvinfer: Fastest Tactic: 1002 Time: 0.127296
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.187104
nvinfer: Tactic: 0 time 0.10352
nvinfer: Fastest Tactic: 0 Time: 0.10352
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.14464
nvinfer: Tactic: 0 time 0.216416
nvinfer: Fastest Tactic: 1002 Time: 0.14464
nvinfer: *************** Autotuning format combination: Float(1,38,1444,144400) -> Float(1,1,1,121296) ***************
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.074656
nvinfer: Tactic: 1 time 0.19104
nvinfer: Fastest Tactic: 0 Time: 0.074656
nvinfer: *************** Autotuning format combination: Float(1,38,1444:32,5776) -> Float(1,1,1:32,3791) ***************
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.094464
nvinfer: Tactic: 1 time 0.33792
nvinfer: Fastest Tactic: 0 Time: 0.094464
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.044224
nvinfer: Tactic: 0 time 0.04704
nvinfer: Fastest Tactic: 1002 Time: 0.044224
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.08768
nvinfer: Tactic: 0 time 0.033984
nvinfer: Fastest Tactic: 0 Time: 0.033984
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.04608
nvinfer: Tactic: 0 time 0.05872
nvinfer: Fastest Tactic: 1002 Time: 0.04608
nvinfer: *************** Autotuning format combination: Float(1,19,361,54150) -> Float(1,1,1,45486) ***************
nvinfer: --------------- Timing Runner: fc7_mbox_conf_perm + fc7_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.028
nvinfer: Tactic: 1 time 0.04864
nvinfer: Fastest Tactic: 0 Time: 0.028
nvinfer: *************** Autotuning format combination: Float(1,19,361:32,1805) -> Float(1,1,1:32,1422) ***************
nvinfer: --------------- Timing Runner: fc7_mbox_conf_perm + fc7_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.03808
nvinfer: Tactic: 1 time 0.115296
nvinfer: Fastest Tactic: 0 Time: 0.03808
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.01776
nvinfer: Tactic: 0 time 0.01664
nvinfer: Fastest Tactic: 0 Time: 0.01664
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.03472
nvinfer: Tactic: 0 time 0.011776
nvinfer: Fastest Tactic: 0 Time: 0.011776
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.02912
nvinfer: Tactic: 0 time 0.01808
nvinfer: Fastest Tactic: 0 Time: 0.01808
nvinfer: *************** Autotuning format combination: Float(1,10,100,15000) -> Float(1,1,1,12600) ***************
nvinfer: --------------- Timing Runner: conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.0104
nvinfer: Tactic: 1 time 0.017344
nvinfer: Fastest Tactic: 0 Time: 0.0104
nvinfer: *************** Autotuning format combination: Float(1,10,100:32,500) -> Float(1,1,1:32,394) ***************
nvinfer: --------------- Timing Runner: conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.01248
nvinfer: Tactic: 1 time 0.039744
nvinfer: Fastest Tactic: 0 Time: 0.01248
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.009024
nvinfer: Tactic: 0 time 0.006944
nvinfer: Fastest Tactic: 0 Time: 0.006944
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.031584
nvinfer: Tactic: 0 time 0.00528
nvinfer: Fastest Tactic: 0 Time: 0.00528
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.008864
nvinfer: Tactic: 0 time 0.00736
nvinfer: Fastest Tactic: 0 Time: 0.00736
nvinfer: *************** Autotuning format combination: Float(1,5,25,3750) -> Float(1,1,1,3150) ***************
nvinfer: --------------- Timing Runner: conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00464
nvinfer: Tactic: 1 time 0.05968
nvinfer: Fastest Tactic: 0 Time: 0.00464
nvinfer: *************** Autotuning format combination: Float(1,5,25:32,125) -> Float(1,1,1:32,99) ***************
nvinfer: --------------- Timing Runner: conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.005024
nvinfer: Tactic: 1 time 0.017376
nvinfer: Fastest Tactic: 0 Time: 0.005024
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.007456
nvinfer: Tactic: 0 time 0.00368
nvinfer: Fastest Tactic: 0 Time: 0.00368
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.0216
nvinfer: Tactic: 0 time 0.00336
nvinfer: Fastest Tactic: 0 Time: 0.00336
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.008384
nvinfer: Tactic: 0 time 0.004576
nvinfer: Fastest Tactic: 0 Time: 0.004576
nvinfer: *************** Autotuning format combination: Float(1,3,9,900) -> Float(1,1,1,756) ***************
nvinfer: --------------- Timing Runner: conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.004736
nvinfer: Tactic: 1 time 0.009024
nvinfer: Fastest Tactic: 0 Time: 0.004736
nvinfer: *************** Autotuning format combination: Float(1,3,9:32,36) -> Float(1,1,1:32,24) ***************
nvinfer: --------------- Timing Runner: conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00336
nvinfer: Tactic: 1 time 0.063744
nvinfer: Fastest Tactic: 0 Time: 0.00336
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00736
nvinfer: Tactic: 0 time 0.003456
nvinfer: Fastest Tactic: 0 Time: 0.003456
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.006816
nvinfer: Tactic: 0 time 0.003424
nvinfer: Fastest Tactic: 0 Time: 0.003424
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.00672
nvinfer: Tactic: 0 time 0.00304
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: *************** Autotuning format combination: Float(1,1,1,100) -> Float(1,1,1,84) ***************
nvinfer: --------------- Timing Runner: conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00304
nvinfer: Tactic: 1 time 0.00704
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: *************** Autotuning format combination: Float(1,1,1:32,4) -> Float(1,1,1:32,3) ***************
nvinfer: --------------- Timing Runner: conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat (Shuffle)
nvinfer: Tactic: 0 time 0.00304
nvinfer: Tactic: 1 time 0.013024
nvinfer: Fastest Tactic: 0 Time: 0.00304
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.08192
nvinfer: Tactic: 0 time 0.036576
nvinfer: Fastest Tactic: 0 Time: 0.036576
nvinfer: --------------- Timing Runner: conv4_3_norm_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.1824
nvinfer: Tactic: 0 time 0.077504
nvinfer: Fastest Tactic: 0 Time: 0.077504
nvinfer: --------------- Timing Runner: fc7_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.037184
nvinfer: Tactic: 0 time 0.007584
nvinfer: Fastest Tactic: 0 Time: 0.007584
nvinfer: --------------- Timing Runner: fc7_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.072
nvinfer: Tactic: 0 time 0.030784
nvinfer: Fastest Tactic: 0 Time: 0.030784
nvinfer: --------------- Timing Runner: conv6_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.00864
nvinfer: Tactic: 0 time 0.0048
nvinfer: Fastest Tactic: 0 Time: 0.0048
nvinfer: --------------- Timing Runner: conv6_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.02128
nvinfer: Tactic: 0 time 0.010336
nvinfer: Fastest Tactic: 0 Time: 0.010336
nvinfer: --------------- Timing Runner: conv7_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.004416
nvinfer: Tactic: 0 time 0.002784
nvinfer: Fastest Tactic: 0 Time: 0.002784
nvinfer: --------------- Timing Runner: conv7_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.00848
nvinfer: Tactic: 0 time 0.004736
nvinfer: Fastest Tactic: 0 Time: 0.004736
nvinfer: --------------- Timing Runner: conv8_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.0048
nvinfer: Tactic: 0 time 0.002624
nvinfer: Fastest Tactic: 0 Time: 0.002624
nvinfer: --------------- Timing Runner: conv8_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.00928
nvinfer: Tactic: 0 time 0.003296
nvinfer: Fastest Tactic: 0 Time: 0.003296
nvinfer: --------------- Timing Runner: conv9_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.0048
nvinfer: Tactic: 0 time 0.00288
nvinfer: Fastest Tactic: 0 Time: 0.00288
nvinfer: --------------- Timing Runner: conv9_2_mbox_conf_flat copy (Reformat)
nvinfer: Tactic: 1002 time 0.006624
nvinfer: Tactic: 0 time 0.003136
nvinfer: Fastest Tactic: 0 Time: 0.003136
nvinfer: *************** Autotuning format combination: Float(1,1,1,183372) -> Float(1,21,183372) ***************
nvinfer: --------------- Timing Runner: mbox_conf_reshape (Shuffle)
nvinfer: Tactic: 0 time 0.055776
nvinfer: Tactic: 1 time 0.24192
nvinfer: Fastest Tactic: 0 Time: 0.055776
nvinfer: *************** Autotuning format combination: Float(1,21,183372) -> Float(1,21,183372) ***************
nvinfer: --------------- Timing Runner: mbox_conf_softmax (SoftMax)
nvinfer: Tactic: 1001 time 3.38042
nvinfer: Fastest Tactic: 1001 Time: 3.38042
nvinfer: --------------- Timing Runner: mbox_conf_softmax (ExtSoftMax)
nvinfer: Tactic: 0 time 0.256064
nvinfer: Fastest Tactic: 0 Time: 0.256064
nvinfer: >>>>>>>>>>>>>>> Chose Runner Type: ExtSoftMax Tactic: 0
nvinfer: 
nvinfer: *************** Autotuning format combination: Float(1,21,183372) -> Float(1,1,1,183372) ***************
nvinfer: --------------- Timing Runner: mbox_conf_flatten (Shuffle)
nvinfer: Tactic: 0 time 0.06608
nvinfer: Tactic: 1 time 0.2344
nvinfer: Fastest Tactic: 0 Time: 0.06608
nvinfer: --------------- Timing Runner: <reformat> (Reformat)
nvinfer: Tactic: 1002 time 0.04752
nvinfer: Tactic: 0 time 0.02432
nvinfer: Fastest Tactic: 0 Time: 0.02432
nvinfer: *************** Autotuning format combination: Float(1,1,1,34928), Float(1,1,1,183372), Float(1,1,34928,69856) -> Float(1,7,1400,1400), Float(1,1,1,1) ***************
nvinfer: Formats and tactics selection completed in 30.9808 seconds.
nvinfer: After reformat layers: 69 layers
nvinfer: Block size 104857600
nvinfer: Block size 23040000
nvinfer: Block size 23040000
nvinfer: Block size 2880000
nvinfer: Block size 578048
nvinfer: Block size 217088
nvinfer: Block size 184832
nvinfer: Block size 139776
nvinfer: Block size 69632
nvinfer: Block size 19456
nvinfer: Block size 15360
nvinfer: Block size 5120
nvinfer: Block size 4096
nvinfer: Block size 1536
nvinfer: Block size 512
nvinfer: Block size 512
nvinfer: Total Activation Memory: 155053568
nvinfer: Detected 1 inputs and 1 output network tensors.
nvinfer: conv1_1 + relu1_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv1_1 + relu1_1 (type=CaskConvolution, tactic=5137655947464784826)
nvinfer: conv1_2 + relu1_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_relu_tile148m_nt_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv1_2 + relu1_2 (type=CaskConvolution, tactic=5921334924264294896)
nvinfer: Debug synchronize completed successfully after build for layer: pool1 (type=Pooling, tactic=-1)
nvinfer: conv2_1 + relu2_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv2_1 + relu2_1 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv2_2 + relu2_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv2_2 + relu2_2 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: Debug synchronize completed successfully after build for layer: pool2 (type=Pooling, tactic=-1)
nvinfer: conv3_1 + relu3_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv3_1 + relu3_1 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv3_2 + relu3_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv3_2 + relu3_2 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv3_3 + relu3_3 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv3_3 + relu3_3 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: Debug synchronize completed successfully after build for layer: pool3 (type=TiledPooling, tactic=5767425)
nvinfer: conv4_1 + relu4_1 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv4_1 + relu4_1 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv4_2 + relu4_2 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv4_2 + relu4_2 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv4_3 + relu4_3 (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3 + relu4_3 (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm (type=PluginV2, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: Debug synchronize completed successfully after build for layer: pool4 (type=Pooling, tactic=-1)
nvinfer: conv5_1 + relu5_1 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv5_1 + relu5_1 (type=CaskConvolution, tactic=-410470605513481746)
nvinfer: conv5_2 + relu5_2 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv5_2 + relu5_2 (type=CaskConvolution, tactic=-410470605513481746)
nvinfer: conv5_3 + relu5_3 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv5_3 + relu5_3 (type=CaskConvolution, tactic=-410470605513481746)
nvinfer: Debug synchronize completed successfully after build for layer: pool5 (type=TiledPooling, tactic=6553857)
nvinfer: fc6 + relu6 (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_medium_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: fc6 + relu6 (type=CaskConvolution, tactic=4501471010995462441)
nvinfer: fc7 + relu7 (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: fc7 + relu7 (type=CaskConvolution, tactic=-37215280111360163)
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: fc7_mbox_loc || fc7_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_loc || fc7_mbox_conf (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv6_1 + conv6_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_interior_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv6_1 + conv6_1_relu (type=CaskConvolution, tactic=-37215280111360163)
nvinfer: conv6_2 + conv6_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2 + conv6_2_relu (type=CaskConvolution, tactic=5137655947464784826)
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: conv6_2_mbox_loc || conv6_2_mbox_conf (scudnn_winograd) Set Tactic Name: maxwell_scudnn_winograd_128x128_ldg1_ldg4_mobile_relu_tile148t_nt_v0
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_loc || conv6_2_mbox_conf (type=CaskConvolution, tactic=-1343271414618805657)
nvinfer: conv7_1 + conv7_1_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x64_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv7_1 + conv7_1_relu (type=CaskConvolution, tactic=5137655947464784826)
nvinfer: conv7_2 + conv7_2_relu (scudnn) Set Tactic Name: maxwell_scudnn_128x128_relu_small_nn_v1
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2 + conv7_2_relu (type=CaskConvolution, tactic=-410470605513481746)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_loc || conv7_2_mbox_conf (type=FusedConvActConvolution, tactic=10485759)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_1 + conv8_1_relu (type=FusedConvActConvolution, tactic=3997695)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2 + conv8_2_relu (type=FusedConvActConvolution, tactic=7274495)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_loc || conv8_2_mbox_conf (type=FusedConvActConvolution, tactic=2621439)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_1 + conv9_1_relu (type=FusedConvActConvolution, tactic=5177343)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2 + conv9_2_relu (type=FusedConvActConvolution, tactic=7274495)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_priorbox (type=PluginV2, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_loc || conv9_2_mbox_conf (type=FusedConvActConvolution, tactic=7274495)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_loc_perm + fc7_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_priorbox copy (type=Reformat, tactic=1002)
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_priorbox copy (type=Reformat, tactic=1002)
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_priorbox copy (type=Reformat, tactic=1002)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_priorbox copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_priorbox copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_priorbox copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_conf_perm + fc7_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat (type=Shuffle, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv4_3_norm_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: fc7_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv6_2_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv7_2_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv8_2_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: conv9_2_mbox_conf_flat copy (type=Reformat, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: mbox_conf_softmax (type=ExtSoftMax, tactic=0)
nvinfer: Debug synchronize completed successfully after build for layer: detection_out (type=PluginV2, tactic=0)
nvinfer: Layer: conv1_1 + relu1_1 Weights: 0 HostPersistent: 1664 DevicePersistent: 547328
nvinfer: Layer: conv1_2 + relu1_2 Weights: 0 HostPersistent: 512 DevicePersistent: 410112
nvinfer: Layer: pool1 Weights: 0 HostPersistent: 16 DevicePersistent: 0
nvinfer: Layer: conv2_1 + relu2_1 Weights: 0 HostPersistent: 512 DevicePersistent: 819712
nvinfer: Layer: conv2_2 + relu2_2 Weights: 0 HostPersistent: 512 DevicePersistent: 1638912
nvinfer: Layer: pool2 Weights: 0 HostPersistent: 16 DevicePersistent: 0
nvinfer: Layer: conv3_1 + relu3_1 Weights: 0 HostPersistent: 512 DevicePersistent: 3277824
nvinfer: Layer: conv3_2 + relu3_2 Weights: 0 HostPersistent: 512 DevicePersistent: 6554624
nvinfer: Layer: conv3_3 + relu3_3 Weights: 0 HostPersistent: 512 DevicePersistent: 6554624
nvinfer: Layer: pool3 Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv4_1 + relu4_1 Weights: 0 HostPersistent: 512 DevicePersistent: 13109248
nvinfer: Layer: conv4_2 + relu4_2 Weights: 0 HostPersistent: 512 DevicePersistent: 26216448
nvinfer: Layer: conv4_3 + relu4_3 Weights: 0 HostPersistent: 512 DevicePersistent: 26216448
nvinfer: Layer: conv4_3_norm Weights: 0 HostPersistent: 16 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf Weights: 0 HostPersistent: 512 DevicePersistent: 6038016
nvinfer: Layer: pool4 Weights: 0 HostPersistent: 16 DevicePersistent: 0
nvinfer: Layer: conv5_1 + relu5_1 Weights: 0 HostPersistent: 1664 DevicePersistent: 9441792
nvinfer: Layer: conv5_2 + relu5_2 Weights: 0 HostPersistent: 1664 DevicePersistent: 9441792
nvinfer: Layer: conv5_3 + relu5_3 Weights: 0 HostPersistent: 1664 DevicePersistent: 9441792
nvinfer: Layer: pool5 Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: fc6 + relu6 Weights: 0 HostPersistent: 2176 DevicePersistent: 18881024
nvinfer: Layer: fc7 + relu7 Weights: 0 HostPersistent: 3200 DevicePersistent: 4200960
nvinfer: Layer: fc7_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: fc7_mbox_loc || fc7_mbox_conf Weights: 0 HostPersistent: 512 DevicePersistent: 16016384
nvinfer: Layer: conv6_1 + conv6_1_relu Weights: 0 HostPersistent: 3200 DevicePersistent: 1052160
nvinfer: Layer: conv6_2 + conv6_2_relu Weights: 0 HostPersistent: 1664 DevicePersistent: 4721664
nvinfer: Layer: conv6_2_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: conv6_2_mbox_loc || conv6_2_mbox_conf Weights: 0 HostPersistent: 512 DevicePersistent: 8008704
nvinfer: Layer: conv7_1 + conv7_1_relu Weights: 0 HostPersistent: 1664 DevicePersistent: 263680
nvinfer: Layer: conv7_2 + conv7_2_relu Weights: 0 HostPersistent: 1664 DevicePersistent: 1181184
nvinfer: Layer: conv7_2_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: conv7_2_mbox_loc || conv7_2_mbox_conf Weights: 1382400 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_1 + conv8_1_relu Weights: 131072 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2 + conv8_2_relu Weights: 1179648 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_loc || conv8_2_mbox_conf Weights: 921600 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_1 + conv9_1_relu Weights: 131072 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2 + conv9_2_relu Weights: 1179648 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_priorbox Weights: 0 HostPersistent: 24 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_loc || conv9_2_mbox_conf Weights: 921600 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: fc7_mbox_loc_perm + fc7_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: fc7_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv6_2_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv7_2_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_priorbox copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: fc7_mbox_conf_perm + fc7_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv4_3_norm_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: fc7_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv6_2_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv7_2_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv8_2_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: conv9_2_mbox_conf_flat copy Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: mbox_conf_softmax Weights: 0 HostPersistent: 0 DevicePersistent: 0
nvinfer: Layer: detection_out Weights: 0 HostPersistent: 40 DevicePersistent: 0
nvinfer: Total Host Persistent Memory: 26616
nvinfer: Total Device Persistent Memory: 174034432
nvinfer: Total Weight Memory: 5847040
nvinfer: Builder timing cache: created 77 entries, 4 hit(s)
nvinfer: Engine generation completed in 33.8313 seconds.
nvinfer: Engine Layer Information:
nvinfer: Layer(scudnn): conv1_1 + relu1_1, Tactic: 5137655947464784826, data[Float(3,300,300)] -> conv1_1[Float(64,300,300)]
nvinfer: Layer(scudnn_winograd): conv1_2 + relu1_2, Tactic: 5921334924264294896, conv1_1[Float(64,300,300)] -> conv1_2[Float(64,300,300)]
nvinfer: Layer(Pooling): pool1, Tactic: -1, conv1_2[Float(64,300,300)] -> pool1[Float(64,150,150)]
nvinfer: Layer(scudnn_winograd): conv2_1 + relu2_1, Tactic: -1343271414618805657, pool1[Float(64,150,150)] -> conv2_1[Float(128,150,150)]
nvinfer: Layer(scudnn_winograd): conv2_2 + relu2_2, Tactic: -1343271414618805657, conv2_1[Float(128,150,150)] -> conv2_2[Float(128,150,150)]
nvinfer: Layer(Pooling): pool2, Tactic: -1, conv2_2[Float(128,150,150)] -> pool2[Float(128,75,75)]
nvinfer: Layer(scudnn_winograd): conv3_1 + relu3_1, Tactic: -1343271414618805657, pool2[Float(128,75,75)] -> conv3_1[Float(256,75,75)]
nvinfer: Layer(scudnn_winograd): conv3_2 + relu3_2, Tactic: -1343271414618805657, conv3_1[Float(256,75,75)] -> conv3_2[Float(256,75,75)]
nvinfer: Layer(scudnn_winograd): conv3_3 + relu3_3, Tactic: -1343271414618805657, conv3_2[Float(256,75,75)] -> conv3_3[Float(256,75,75)]
nvinfer: Layer(PoolingTiled): pool3, Tactic: 5767425, conv3_3[Float(256,75,75)] -> pool3[Float(256,38,38)]
nvinfer: Layer(scudnn_winograd): conv4_1 + relu4_1, Tactic: -1343271414618805657, pool3[Float(256,38,38)] -> conv4_1[Float(512,38,38)]
nvinfer: Layer(scudnn_winograd): conv4_2 + relu4_2, Tactic: -1343271414618805657, conv4_1[Float(512,38,38)] -> conv4_2[Float(512,38,38)]
nvinfer: Layer(scudnn_winograd): conv4_3 + relu4_3, Tactic: -1343271414618805657, conv4_2[Float(512,38,38)] -> conv4_3[Float(512,38,38)]
nvinfer: Layer(PluginV2): conv4_3_norm, Tactic: 0, conv4_3[Float(512,38,38)] -> conv4_3_norm[Float(512,38,38)]
nvinfer: Layer(PluginV2): conv4_3_norm_mbox_priorbox, Tactic: 0, conv4_3_norm[Float(512,38,38)], data[Float(3,300,300)] -> conv4_3_norm_mbox_priorbox[Float(2,23104,1)]
nvinfer: Layer(scudnn_winograd): conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf, Tactic: -1343271414618805657, conv4_3_norm[Float(512,38,38)] -> conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf[Float(100,38,38)]
nvinfer: Layer(Pooling): pool4, Tactic: -1, conv4_3[Float(512,38,38)] -> pool4[Float(512,19,19)]
nvinfer: Layer(scudnn): conv5_1 + relu5_1, Tactic: -410470605513481746, pool4[Float(512,19,19)] -> conv5_1[Float(512,19,19)]
nvinfer: Layer(scudnn): conv5_2 + relu5_2, Tactic: -410470605513481746, conv5_1[Float(512,19,19)] -> conv5_2[Float(512,19,19)]
nvinfer: Layer(scudnn): conv5_3 + relu5_3, Tactic: -410470605513481746, conv5_2[Float(512,19,19)] -> conv5_3[Float(512,19,19)]
nvinfer: Layer(PoolingTiled): pool5, Tactic: 6553857, conv5_3[Float(512,19,19)] -> pool5[Float(512,19,19)]
nvinfer: Layer(scudnn): fc6 + relu6, Tactic: 4501471010995462441, pool5[Float(512,19,19)] -> fc6[Float(1024,19,19)]
nvinfer: Layer(scudnn): fc7 + relu7, Tactic: -37215280111360163, fc6[Float(1024,19,19)] -> fc7[Float(1024,19,19)]
nvinfer: Layer(PluginV2): fc7_mbox_priorbox, Tactic: 0, fc7[Float(1024,19,19)], data[Float(3,300,300)] -> fc7_mbox_priorbox[Float(2,8664,1)]
nvinfer: Layer(scudnn_winograd): fc7_mbox_loc || fc7_mbox_conf, Tactic: -1343271414618805657, fc7[Float(1024,19,19)] -> fc7_mbox_loc || fc7_mbox_conf[Float(150,19,19)]
nvinfer: Layer(scudnn): conv6_1 + conv6_1_relu, Tactic: -37215280111360163, fc7[Float(1024,19,19)] -> conv6_1[Float(256,19,19)]
nvinfer: Layer(scudnn): conv6_2 + conv6_2_relu, Tactic: 5137655947464784826, conv6_1[Float(256,19,19)] -> conv6_2[Float(512,10,10)]
nvinfer: Layer(PluginV2): conv6_2_mbox_priorbox, Tactic: 0, conv6_2[Float(512,10,10)], data[Float(3,300,300)] -> conv6_2_mbox_priorbox[Float(2,2400,1)]
nvinfer: Layer(scudnn_winograd): conv6_2_mbox_loc || conv6_2_mbox_conf, Tactic: -1343271414618805657, conv6_2[Float(512,10,10)] -> conv6_2_mbox_loc || conv6_2_mbox_conf[Float(150,10,10)]
nvinfer: Layer(scudnn): conv7_1 + conv7_1_relu, Tactic: 5137655947464784826, conv6_2[Float(512,10,10)] -> conv7_1[Float(128,10,10)]
nvinfer: Layer(scudnn): conv7_2 + conv7_2_relu, Tactic: -410470605513481746, conv7_1[Float(128,10,10)] -> conv7_2[Float(256,5,5)]
nvinfer: Layer(PluginV2): conv7_2_mbox_priorbox, Tactic: 0, conv7_2[Float(256,5,5)], data[Float(3,300,300)] -> conv7_2_mbox_priorbox[Float(2,600,1)]
nvinfer: Layer(FusedConvActDirect): conv7_2_mbox_loc || conv7_2_mbox_conf, Tactic: 10485759, conv7_2[Float(256,5,5)] -> conv7_2_mbox_loc || conv7_2_mbox_conf[Float(150,5,5)]
nvinfer: Layer(FusedConvActDirect): conv8_1 + conv8_1_relu, Tactic: 3997695, conv7_2[Float(256,5,5)] -> conv8_1[Float(128,5,5)]
nvinfer: Layer(FusedConvActDirect): conv8_2 + conv8_2_relu, Tactic: 7274495, conv8_1[Float(128,5,5)] -> conv8_2[Float(256,3,3)]
nvinfer: Layer(PluginV2): conv8_2_mbox_priorbox, Tactic: 0, conv8_2[Float(256,3,3)], data[Float(3,300,300)] -> conv8_2_mbox_priorbox[Float(2,144,1)]
nvinfer: Layer(FusedConvActDirect): conv8_2_mbox_loc || conv8_2_mbox_conf, Tactic: 2621439, conv8_2[Float(256,3,3)] -> conv8_2_mbox_loc || conv8_2_mbox_conf[Float(100,3,3)]
nvinfer: Layer(FusedConvActDirect): conv9_1 + conv9_1_relu, Tactic: 5177343, conv8_2[Float(256,3,3)] -> conv9_1[Float(128,3,3)]
nvinfer: Layer(FusedConvActDirect): conv9_2 + conv9_2_relu, Tactic: 7274495, conv9_1[Float(128,3,3)] -> conv9_2[Float(256,1,1)]
nvinfer: Layer(PluginV2): conv9_2_mbox_priorbox, Tactic: 0, conv9_2[Float(256,1,1)], data[Float(3,300,300)] -> conv9_2_mbox_priorbox[Float(2,16,1)]
nvinfer: Layer(FusedConvActDirect): conv9_2_mbox_loc || conv9_2_mbox_conf, Tactic: 7274495, conv9_2[Float(256,1,1)] -> conv9_2_mbox_loc || conv9_2_mbox_conf[Float(100,1,1)]
nvinfer: Layer(Shuffle): conv4_3_norm_mbox_loc_perm + conv4_3_norm_mbox_loc_flat, Tactic: 0, conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf[Float(16,38,38)] -> mbox_loc[Float(23104,1,1)]
nvinfer: Layer(Shuffle): fc7_mbox_loc_perm + fc7_mbox_loc_flat, Tactic: 0, fc7_mbox_loc || fc7_mbox_conf[Float(24,19,19)] -> mbox_loc[Float(8664,1,1)]
nvinfer: Layer(Shuffle): conv6_2_mbox_loc_perm + conv6_2_mbox_loc_flat, Tactic: 0, conv6_2_mbox_loc || conv6_2_mbox_conf[Float(24,10,10)] -> mbox_loc[Float(2400,1,1)]
nvinfer: Layer(Shuffle): conv7_2_mbox_loc_perm + conv7_2_mbox_loc_flat, Tactic: 0, conv7_2_mbox_loc || conv7_2_mbox_conf[Float(24,5,5)] -> mbox_loc[Float(600,1,1)]
nvinfer: Layer(Shuffle): conv8_2_mbox_loc_perm + conv8_2_mbox_loc_flat, Tactic: 0, conv8_2_mbox_loc || conv8_2_mbox_conf[Float(16,3,3)] -> mbox_loc[Float(144,1,1)]
nvinfer: Layer(Shuffle): conv9_2_mbox_loc_perm + conv9_2_mbox_loc_flat, Tactic: 0, conv9_2_mbox_loc || conv9_2_mbox_conf[Float(16,1,1)] -> mbox_loc[Float(16,1,1)]
nvinfer: Layer(Reformat): conv4_3_norm_mbox_priorbox copy, Tactic: 1002, conv4_3_norm_mbox_priorbox[Float(2,23104,1)] -> mbox_priorbox[Float(2,23104,1)]
nvinfer: Layer(Reformat): fc7_mbox_priorbox copy, Tactic: 1002, fc7_mbox_priorbox[Float(2,8664,1)] -> mbox_priorbox[Float(2,8664,1)]
nvinfer: Layer(Reformat): conv6_2_mbox_priorbox copy, Tactic: 1002, conv6_2_mbox_priorbox[Float(2,2400,1)] -> mbox_priorbox[Float(2,2400,1)]
nvinfer: Layer(Reformat): conv7_2_mbox_priorbox copy, Tactic: 0, conv7_2_mbox_priorbox[Float(2,600,1)] -> mbox_priorbox[Float(2,600,1)]
nvinfer: Layer(Reformat): conv8_2_mbox_priorbox copy, Tactic: 0, conv8_2_mbox_priorbox[Float(2,144,1)] -> mbox_priorbox[Float(2,144,1)]
nvinfer: Layer(Reformat): conv9_2_mbox_priorbox copy, Tactic: 0, conv9_2_mbox_priorbox[Float(2,16,1)] -> mbox_priorbox[Float(2,16,1)]
nvinfer: Layer(Shuffle): conv4_3_norm_mbox_conf_perm + conv4_3_norm_mbox_conf_flat, Tactic: 0, conv4_3_norm_mbox_loc || conv4_3_norm_mbox_conf[Float(84,38,38)] -> conv4_3_norm_mbox_conf_flat[Float(121296,1,1)]
nvinfer: Layer(Shuffle): fc7_mbox_conf_perm + fc7_mbox_conf_flat, Tactic: 0, fc7_mbox_loc || fc7_mbox_conf[Float(126,19,19)] -> fc7_mbox_conf_flat[Float(45486,1,1)]
nvinfer: Layer(Shuffle): conv6_2_mbox_conf_perm + conv6_2_mbox_conf_flat, Tactic: 0, conv6_2_mbox_loc || conv6_2_mbox_conf[Float(126,10,10)] -> conv6_2_mbox_conf_flat[Float(12600,1,1)]
nvinfer: Layer(Shuffle): conv7_2_mbox_conf_perm + conv7_2_mbox_conf_flat, Tactic: 0, conv7_2_mbox_loc || conv7_2_mbox_conf[Float(126,5,5)] -> conv7_2_mbox_conf_flat[Float(3150,1,1)]
nvinfer: Layer(Shuffle): conv8_2_mbox_conf_perm + conv8_2_mbox_conf_flat, Tactic: 0, conv8_2_mbox_loc || conv8_2_mbox_conf[Float(84,3,3)] -> conv8_2_mbox_conf_flat[Float(756,1,1)]
nvinfer: Layer(Shuffle): conv9_2_mbox_conf_perm + conv9_2_mbox_conf_flat, Tactic: 0, conv9_2_mbox_loc || conv9_2_mbox_conf[Float(84,1,1)] -> conv9_2_mbox_conf_flat[Float(84,1,1)]
nvinfer: Layer(Reformat): conv4_3_norm_mbox_conf_flat copy, Tactic: 0, conv4_3_norm_mbox_conf_flat[Float(121296,1,1)] -> mbox_conf[Float(121296,1,1)]
nvinfer: Layer(Reformat): fc7_mbox_conf_flat copy, Tactic: 0, fc7_mbox_conf_flat[Float(45486,1,1)] -> mbox_conf[Float(45486,1,1)]
nvinfer: Layer(Reformat): conv6_2_mbox_conf_flat copy, Tactic: 0, conv6_2_mbox_conf_flat[Float(12600,1,1)] -> mbox_conf[Float(12600,1,1)]
nvinfer: Layer(Reformat): conv7_2_mbox_conf_flat copy, Tactic: 0, conv7_2_mbox_conf_flat[Float(3150,1,1)] -> mbox_conf[Float(3150,1,1)]
nvinfer: Layer(Reformat): conv8_2_mbox_conf_flat copy, Tactic: 0, conv8_2_mbox_conf_flat[Float(756,1,1)] -> mbox_conf[Float(756,1,1)]
nvinfer: Layer(Reformat): conv9_2_mbox_conf_flat copy, Tactic: 0, conv9_2_mbox_conf_flat[Float(84,1,1)] -> mbox_conf[Float(84,1,1)]
nvinfer: Layer(ExtSoftMax): mbox_conf_softmax, Tactic: 0, mbox_conf_reshape[Float(8732,21)] -> mbox_conf_softmax[Float(8732,21)]
nvinfer: Layer(PluginV2): detection_out, Tactic: 0, mbox_loc[Float(34928,1,1)], mbox_conf_flatten[Float(183372,1,1)], mbox_priorbox[Float(2,34928,1)] -> detection_out[Float(1,200,7)], keep_count[Float(1,1,1)]
Engine is built, destroying the parser
Serializing the engine
Serialized, destroying the engine
Done with engine conversion
Creating runtime
Deserializing the engine
nvinfer: Deserialize required 1935434 microseconds.
Creating execution context
Evaluating bindings
Copying the inputs
Executing
Copying the output
Processing the output
0: 0 7 0.0993622 0.789838 0.789838 1 1 
7: 0 17 0.0968407 0.0226227 0.902623 0.164044 1 
14: 0 7 0.0720833 0.256505 0.683172 0.703495 1 
21: 0 17 0.0333011 0.1 0.1 0.2 0.2 
28: 0 1 0.0332599 0.896667 0.336667 0.996667 0.436667 
35: 0 1 0.0317572 0.816667 0.336667 0.916667 0.436667 
42: 0 17 0.0272164 0.0492893 0.849289 0.190711 0.990711 
49: 0 7 0.0253817 0.669185 0.751704 0.930815 1 
56: 0 7 0.0251204 0.00503713 0.775852 0.528296 1 
63: 0 5 0.024691 0.1 0.1 0.2 0.2 
70: 0 7 0.0242802 0.721667 0.615 1 0.985 
77: 0 1 0.023664 0.923333 0.283333 1 0.383333 
84: 0 1 0.0232848 0.87 0.283333 0.97 0.383333 
91: 0 7 0.0221862 0.475956 0.929289 0.617377 1 
98: 0 7 0.0197431 0.135852 0.645037 0.397481 1 
105: 0 1 0.0184194 0.95 0.336667 1 0.436667 
112: 0 17 0.0181959 0.0226227 0.795956 0.164044 0.937377 
119: 0 7 0.017726 0.1 0.1 0.2 0.2 
126: 0 1 0.0172585 0.816667 0.283333 0.916667 0.383333 
133: 0 1 0.0169653 0.923333 0.23 1 0.33 
140: 0 7 0.0166899 0.53837 0.882519 1 1 
147: 0 17 0.0154587 0.102623 0.902623 0.244044 1 
154: 0 17 0.0154537 0.0166667 0.87 0.116667 0.97 
161: 0 7 0.0152249 0.325037 0.775852 0.848296 1 
168: 0 1 0.014493 0.87 0.23 0.97 0.33 
175: 0 15 0.0140088 0.449289 0.742623 0.590711 0.884044 
182: 0 1 0.0131713 0 0.31 0.0633333 0.41 
189: 0 17 0.0125726 0.15 0.816667 0.25 0.916667 
196: 0 17 0.0124006 0.0966667 0.816667 0.196667 0.916667 
203: 0 1 0.0122645 0.656667 0.256667 0.756667 0.356667 
210: 0 1 0.0115151 0 0.256667 0.0633333 0.356667 
217: 0 1 0.0112877 0.923333 0.176667 1 0.276667 
224: 0 4 0.0107744 0.95 0.23 1 0.33 
231: 0 7 0.010742 0.315956 0.849289 0.457377 0.990711 
238: 0 15 0.0106169 0.342623 0.875956 0.484044 1 
245: 0 1 0.0105978 0.576667 0.31 0.676667 0.41 
252: 0 1 0.0104946 0.763333 0.336667 0.863333 0.436667 
259: 0 4 0.0104342 0.87 0.176667 0.97 0.276667 
266: 0 15 0.0103262 0.55 0.87 0.65 0.97 
273: 0 1 0.0102203 0.87 0.176667 0.97 0.276667 
280: 0 15 0.0102108 0.1 0.1 0.2 0.2 
287: 0 15 0.0101353 0.603333 0.87 0.703333 0.97 
294: 0 1 0.0100241 0.63 0.31 0.73 0.41 
301: 0 -1 0 0 0 0 0 
308: 0 -1 0 0 0 0 0 
315: 0 -1 0 0 0 0 0 
322: 0 -1 0 0 0 0 0 
329: 0 -1 0 0 0 0 0 
336: 0 -1 0 0 0 0 0 
343: 0 -1 0 0 0 0 0 
350: 0 -1 0 0 0 0 0 
357: 0 -1 0 0 0 0 0 
364: 0 -1 0 0 0 0 0 
371: 0 -1 0 0 0 0 0 
378: 0 -1 0 0 0 0 0 
385: 0 -1 0 0 0 0 0 
392: 0 -1 0 0 0 0 0 
399: 0 -1 0 0 0 0 0 
406: 0 -1 0 0 0 0 0 
413: 0 -1 0 0 0 0 0 
420: 0 -1 0 0 0 0 0 
427: 0 -1 0 0 0 0 0 
434: 0 -1 0 0 0 0 0 
441: 0 -1 0 0 0 0 0 
448: 0 -1 0 0 0 0 0 
455: 0 -1 0 0 0 0 0 
462: 0 -1 0 0 0 0 0 
469: 0 -1 0 0 0 0 0 
476: 0 -1 0 0 0 0 0 
483: 0 -1 0 0 0 0 0 
490: 0 -1 0 0 0 0 0 
497: 0 -1 0 0 0 0 0 
504: 0 -1 0 0 0 0 0 
511: 0 -1 0 0 0 0 0 
518: 0 -1 0 0 0 0 0 
525: 0 -1 0 0 0 0 0 
532: 0 -1 0 0 0 0 0 
539: 0 -1 0 0 0 0 0 
546: 0 -1 0 0 0 0 0 
553: 0 -1 0 0 0 0 0 
560: 0 -1 0 0 0 0 0 
567: 0 -1 0 0 0 0 0 
574: 0 -1 0 0 0 0 0 
581: 0 -1 0 0 0 0 0 
588: 0 -1 0 0 0 0 0 
595: 0 -1 0 0 0 0 0 
602: 0 -1 0 0 0 0 0 
609: 0 -1 0 0 0 0 0 
616: 0 -1 0 0 0 0 0 
623: 0 -1 0 0 0 0 0 
630: 0 -1 0 0 0 0 0 
637: 0 -1 0 0 0 0 0 
644: 0 -1 0 0 0 0 0 
651: 0 -1 0 0 0 0 0 
658: 0 -1 0 0 0 0 0 
665: 0 -1 0 0 0 0 0 
672: 0 -1 0 0 0 0 0 
679: 0 -1 0 0 0 0 0 
686: 0 -1 0 0 0 0 0 
693: 0 -1 0 0 0 0 0 
700: 0 -1 0 0 0 0 0 
707: 0 -1 0 0 0 0 0 
714: 0 -1 0 0 0 0 0 
721: 0 -1 0 0 0 0 0 
728: 0 -1 0 0 0 0 0 
735: 0 -1 0 0 0 0 0 
742: 0 -1 0 0 0 0 0 
749: 0 -1 0 0 0 0 0 
756: 0 -1 0 0 0 0 0 
763: 0 -1 0 0 0 0 0 
770: 0 -1 0 0 0 0 0 
777: 0 -1 0 0 0 0 0 
784: 0 -1 0 0 0 0 0 
791: 0 -1 0 0 0 0 0 
798: 0 -1 0 0 0 0 0 
805: 0 -1 0 0 0 0 0 
812: 0 -1 0 0 0 0 0 
819: 0 -1 0 0 0 0 0 
826: 0 -1 0 0 0 0 0 
833: 0 -1 0 0 0 0 0 
840: 0 -1 0 0 0 0 0 
847: 0 -1 0 0 0 0 0 
854: 0 -1 0 0 0 0 0 
861: 0 -1 0 0 0 0 0 
868: 0 -1 0 0 0 0 0 
875: 0 -1 0 0 0 0 0 
882: 0 -1 0 0 0 0 0 
889: 0 -1 0 0 0 0 0 
896: 0 -1 0 0 0 0 0 
903: 0 -1 0 0 0 0 0 
910: 0 -1 0 0 0 0 0 
917: 0 -1 0 0 0 0 0 
924: 0 -1 0 0 0 0 0 
931: 0 -1 0 0 0 0 0 
938: 0 -1 0 0 0 0 0 
945: 0 -1 0 0 0 0 0 
952: 0 -1 0 0 0 0 0 
959: 0 -1 0 0 0 0 0 
966: 0 -1 0 0 0 0 0 
973: 0 -1 0 0 0 0 0 
980: 0 -1 0 0 0 0 0 
987: 0 -1 0 0 0 0 0 
994: 0 -1 0 0 0 0 0 
1001: 0 -1 0 0 0 0 0 
1008: 0 -1 0 0 0 0 0 
1015: 0 -1 0 0 0 0 0 
1022: 0 -1 0 0 0 0 0 
1029: 0 -1 0 0 0 0 0 
1036: 0 -1 0 0 0 0 0 
1043: 0 -1 0 0 0 0 0 
1050: 0 -1 0 0 0 0 0 
1057: 0 -1 0 0 0 0 0 
1064: 0 -1 0 0 0 0 0 
1071: 0 -1 0 0 0 0 0 
1078: 0 -1 0 0 0 0 0 
1085: 0 -1 0 0 0 0 0 
1092: 0 -1 0 0 0 0 0 
1099: 0 -1 0 0 0 0 0 
1106: 0 -1 0 0 0 0 0 
1113: 0 -1 0 0 0 0 0 
1120: 0 -1 0 0 0 0 0 
1127: 0 -1 0 0 0 0 0 
1134: 0 -1 0 0 0 0 0 
1141: 0 -1 0 0 0 0 0 
1148: 0 -1 0 0 0 0 0 
1155: 0 -1 0 0 0 0 0 
1162: 0 -1 0 0 0 0 0 
1169: 0 -1 0 0 0 0 0 
1176: 0 -1 0 0 0 0 0 
1183: 0 -1 0 0 0 0 0 
1190: 0 -1 0 0 0 0 0 
1197: 0 -1 0 0 0 0 0 
1204: 0 -1 0 0 0 0 0 
1211: 0 -1 0 0 0 0 0 
1218: 0 -1 0 0 0 0 0 
1225: 0 -1 0 0 0 0 0 
1232: 0 -1 0 0 0 0 0 
1239: 0 -1 0 0 0 0 0 
1246: 0 -1 0 0 0 0 0 
1253: 0 -1 0 0 0 0 0 
1260: 0 -1 0 0 0 0 0 
1267: 0 -1 0 0 0 0 0 
1274: 0 -1 0 0 0 0 0 
1281: 0 -1 0 0 0 0 0 
1288: 0 -1 0 0 0 0 0 
1295: 0 -1 0 0 0 0 0 
1302: 0 -1 0 0 0 0 0 
1309: 0 -1 0 0 0 0 0 
1316: 0 -1 0 0 0 0 0 
1323: 0 -1 0 0 0 0 0 
1330: 0 -1 0 0 0 0 0 
1337: 0 -1 0 0 0 0 0 
1344: 0 -1 0 0 0 0 0 
1351: 0 -1 0 0 0 0 0 
1358: 0 -1 0 0 0 0 0 
1365: 0 -1 0 0 0 0 0 
1372: 0 -1 0 0 0 0 0 
1379: 0 -1 0 0 0 0 0 
1386: 0 -1 0 0 0 0 0 
1393: 0 -1 0 0 0 0 0