diff --git a/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi b/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
index 302cce122..4b6d4d500 100644
--- a/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
+++ b/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
@@ -37,7 +37,7 @@
 				nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
 				nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
 				nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
-				nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0xf0 0x5a 0x5a 0x0 0x0>,
+				/*nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0xf0 0x5a 0x5a 0x0 0x0>,
 						      <TEGRA_DSI_DELAY_MS 5>,
 						      <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0 CMD_NOT_CLUBBED>,
 						      <TEGRA_DSI_DELAY_MS 5>,
@@ -45,7 +45,210 @@
 						      <TEGRA_DSI_DELAY_MS 10>,
 						      <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x4 0x0 0x0 0xc3 0x40 0x00 0x28 0x0 0x0>,
 						      <TEGRA_DSI_DELAY_MS 170>;
-				nvidia,dsi-n-init-cmd = <8>;
+				nvidia,dsi-n-init-cmd = <8>;*/
+				nvidia,dsi-init-cmd =  <TEGRA_DSI_DELAY_MS 10>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE1 0x93 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE2 0x65 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE3 0xF8 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x3C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x3C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x74 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0xF7 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0xF7 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0xF1 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x23 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x09 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x04 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x70 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0xFF 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0xFF 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x7F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x06 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0xA0 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1E 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x0B 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x28 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0xA9 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x59 0x0A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5A 0x2D 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x1A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x15 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x7F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x69 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x59 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x4C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x47 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x38 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x3D 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x27 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x41 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x5B 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x46 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x49 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x3A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6C 0x34 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x25 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x15 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x02 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x70 0x7F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x71 0x69 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x72 0x59 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x73 0x4C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x74 0x47 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0x38 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x3D 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x27 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x41 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x79 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7A 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7B 0x5B 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7C 0x46 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7D 0x49 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7E 0x3A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7F 0x34 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x25 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x81 0x15 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x82 0x02 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x02 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x50 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x52 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x77 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x05 0x57 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x06 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x07 0x4E 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x4C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0A 0x4A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0B 0x48 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0D 0x46 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x44 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0F 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x10 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x12 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x14 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x15 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x16 0x51 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x53 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x77 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0x57 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1D 0x4F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1E 0x4D 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1F 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x4B 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x49 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x23 0x47 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0x45 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x25 0x41 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x26 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x27 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x28 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2A 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x5F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2C 0x01 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2F 0x13 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x17 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x17 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x32 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x33 0x0D 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x34 0x0F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x05 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x07 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x09 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x0B 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3B 0x11 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x42 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x12 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x46 0x17 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x47 0x17 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x48 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x49 0x0C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4A 0x0E 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4B 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4C 0x04 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4D 0x06 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4E 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4F 0x08 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x0A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x10 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x54 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x56 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0x1F 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x58 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x10 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x06 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x40 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x03 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x04 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x6C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x6C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x75 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x08 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0xB4 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x08 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x6C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x6C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x0C 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x88 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0xBB 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x05 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x2A 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x04 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x11 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x48 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x08 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x03 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x03 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
+				<TEGRA_DSI_DELAY_MS 120>,
+				<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>,
+				<TEGRA_DSI_DELAY_MS 5>;
+				nvidia,dsi-n-init-cmd = <202>;
 				disp-default-out {
 					nvidia,out-type = <TEGRA_DC_OUT_DSI>;
 					nvidia,out-width = <107>;
