tegra-xusb 3610000.xhci: exiting ELPG
tegra-xusb 3610000.xhci: Firmware timestamp: 2020-09-11 16:55:03 UTC, Version: 60.09 release
tegra-xusb 3610000.xhci: // Setting command ring address to 0xffede001
tegra-xusb 3610000.xhci: xhci_resume: starting port polling.
tegra-xusb 3610000.xhci: xhci_hub_status_data: stopping port polling.
tegra-xusb 3610000.xhci: exiting ELPG done
tegra-xusb 3610000.xhci: Port Status Change Event for port 7
tegra-xusb 3610000.xhci: resume root hub
tegra-xusb 3610000.xhci: port resume event for port 7
tegra-xusb 3610000.xhci: resume HS port 7
tegra-xusb 3610000.xhci: handle_port_status: starting port polling.
usb usb2: usb wakeup-resume
usb usb2: usb auto-resume
hub 2-0:1.0: hub_resume
tegra-xusb 3610000.xhci: get port status, actual port 0 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x2a0
tegra-xusb 3610000.xhci: get port status, actual port 1 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x2a0
tegra-xusb 3610000.xhci: get port status, actual port 2 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x2a0
tegra-xusb 3610000.xhci: get port status, actual port 3 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x2a0
usb usb1: usb wakeup-resume
usb usb1: usb auto-resume
hub 1-0:1.0: hub_resume
tegra-xusb 3610000.xhci: get port status, actual port 0 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x100
tegra-xusb 3610000.xhci: get port status, actual port 1 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x100
tegra-xusb 3610000.xhci: Resume USB2 port 3
tegra-xusb 3610000.xhci: Port Status Change Event for port 7
tegra-xusb 3610000.xhci: get port status, actual port 2 status  = 0xfe3
tegra-xusb 3610000.xhci: Get port status returned 0x40503
usb usb1-port3: status 0503 change 0004
tegra-xusb 3610000.xhci: get port status, actual port 3 status  = 0x2a0
tegra-xusb 3610000.xhci: Get port status returned 0x100
hub 2-0:1.0: state 7 ports 4 chg 0000 evt 0000
hub 1-0:1.0: state 7 ports 4 chg 0008 evt 0008
tegra-xusb 3610000.xhci: get port status, actual port 2 status  = 0x400e03
tegra-xusb 3610000.xhci: Get port status returned 0x40503
tegra-xusb 3610000.xhci: clear port suspend/resume change, actual port 2 status  = 0xe03
tegra-xusb 3610000.xhci: set port remote wake mask, actual port 0 status  = 0xe0002a0
tegra-xusb 3610000.xhci: xhci_hub_status_data: stopping port polling.
tegra-xusb 3610000.xhci: set port remote wake mask, actual port 1 status  = 0xe0002a0
usb 1-3: usb wakeup-resume
tegra-xusb 3610000.xhci: get port status, actual port 2 status  = 0xe03
tegra-xusb 3610000.xhci: Get port status returned 0x503
tegra-xusb 3610000.xhci: set port remote wake mask, actual port 2 status  = 0xe0002a0
tegra-xusb 3610000.xhci: set port remote wake mask, actual port 3 status  = 0xe0002a0
usb 1-3: Waited 0ms for CONNECT
usb 1-3: finish resume
hub 2-0:1.0: hub_suspend
usb usb2: bus auto-suspend, wakeup 1
tegra-xusb 3610000.xhci: xhci_hub_status_data: stopping port polling.
usb usb2: usb_suspend_both: status 0
hub 1-3:1.0: hub_resume
usb 1-3-port1: status 0101 change 0001
usb usb1-port3: resume, status 0
usb usb1-port3: status 0503, change 0004, 480 Mb/s
hub 1-3:1.0: state 7 ports 7 chg 0002 evt 0000
usb 1-3-port1: status 0101, change 0000, 12 Mb/s
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Slot 2 output ctx = 0xffecb000 (dma)
tegra-xusb 3610000.xhci: Slot 2 input ctx = 0xffece000 (dma)
tegra-xusb 3610000.xhci: Set slot id 2 dcbaa entry ffffff800a9bd010 to 0xffecb000
usb 1-3.1: new high-speed USB device number 5 using tegra-xusb
tegra-xusb 3610000.xhci: Set root hub portnum to 7
tegra-xusb 3610000.xhci: Set fake root hub portnum to 3
tegra-xusb 3610000.xhci: udev->tt =           (null)
tegra-xusb 3610000.xhci: udev->ttport = 0x0
tegra-xusb 3610000.xhci: Slot ID 2 Input Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000003 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful setup address command
tegra-xusb 3610000.xhci: Op regs DCBAA ptr = 0x000000ffedf000
tegra-xusb 3610000.xhci: Slot ID 2 dcbaa entry @ffffff800a9bd010 = 0x000000ffecb000
tegra-xusb 3610000.xhci: Output Context DMA address = 0xffecb000
tegra-xusb 3610000.xhci: Slot ID 2 Input Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000003 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot ID 2 Output Context:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x10000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x020103 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Internal device address = 2
tegra-xusb 3610000.xhci: Endpoint 0x0 ep reset callback called
usb 1-3.1: USB quirks for this device: 400
usb 1-3.1: skipped 3 descriptors after interface
tegra-xusb 3610000.xhci: Waiting for status stage event
usb 1-3.1: default language 0x0409
tegra-xusb 3610000.xhci: Waiting for status stage event
tegra-xusb 3610000.xhci: Waiting for status stage event
tegra-xusb 3610000.xhci: Waiting for status stage event
usb 1-3.1: udev 5, busnum 1, minor = 4
usb 1-3.1: New USB device found, idVendor=0bda, idProduct=8153
usb 1-3.1: New USB device strings: Mfr=1, Product=2, SerialNumber=6
usb 1-3.1: Product: USB 10/100/1000 LAN
usb 1-3.1: Manufacturer: Realtek
usb 1-3.1: SerialNumber: 000001
usb 1-3.1: usb_probe_device
usb 1-3.1: configuration #2 chosen from 2 choices
tegra-xusb 3610000.xhci: add ep 0x83, slot id 2, new drop flags = 0x0, new add flags = 0x80
tegra-xusb 3610000.xhci: xhci_check_bandwidth called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: New Input Control Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000081 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800adae140 (virt) @ffece140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae144 (virt) @ffece144 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae148 (virt) @ffece148 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae150 (virt) @ffece150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae154 (virt) @ffece154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae158 (virt) @ffece158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae15c (virt) @ffece15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae160 (virt) @ffece160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae168 (virt) @ffece168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae170 (virt) @ffece170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae178 (virt) @ffece178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800adae180 (virt) @ffece180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae184 (virt) @ffece184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae188 (virt) @ffece188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae190 (virt) @ffece190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae194 (virt) @ffece194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae198 (virt) @ffece198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae19c (virt) @ffece19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1a0 (virt) @ffece1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1a8 (virt) @ffece1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1b0 (virt) @ffece1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1b8 (virt) @ffece1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800adae1c0 (virt) @ffece1c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae1c4 (virt) @ffece1c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae1c8 (virt) @ffece1c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae1d0 (virt) @ffece1d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae1d4 (virt) @ffece1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae1d8 (virt) @ffece1d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae1dc (virt) @ffece1dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1e0 (virt) @ffece1e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1e8 (virt) @ffece1e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1f0 (virt) @ffece1f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1f8 (virt) @ffece1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800adae200 (virt) @ffece200 (dma) 0x070000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae204 (virt) @ffece204 (dma) 0x10003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae208 (virt) @ffece208 (dma) 0xffebe001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae210 (virt) @ffece210 (dma) 0x100010 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae214 (virt) @ffece214 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae218 (virt) @ffece218 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae21c (virt) @ffece21c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae220 (virt) @ffece220 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae228 (virt) @ffece228 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae230 (virt) @ffece230 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae238 (virt) @ffece238 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful Endpoint Configure command
tegra-xusb 3610000.xhci: Output context after successful config ep cmd:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x18000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x1020203 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc241 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x8000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800bfae100 (virt) @ffecb100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae104 (virt) @ffecb104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae108 (virt) @ffecb108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae110 (virt) @ffecb110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae114 (virt) @ffecb114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae118 (virt) @ffecb118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae11c (virt) @ffecb11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae120 (virt) @ffecb120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae128 (virt) @ffecb128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae130 (virt) @ffecb130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae138 (virt) @ffecb138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800bfae140 (virt) @ffecb140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae144 (virt) @ffecb144 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae148 (virt) @ffecb148 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae150 (virt) @ffecb150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae154 (virt) @ffecb154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae158 (virt) @ffecb158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae15c (virt) @ffecb15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae160 (virt) @ffecb160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae168 (virt) @ffecb168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae170 (virt) @ffecb170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae178 (virt) @ffecb178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800bfae180 (virt) @ffecb180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae184 (virt) @ffecb184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae188 (virt) @ffecb188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae190 (virt) @ffecb190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae194 (virt) @ffecb194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae198 (virt) @ffecb198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae19c (virt) @ffecb19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1a0 (virt) @ffecb1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1a8 (virt) @ffecb1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1b0 (virt) @ffecb1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1b8 (virt) @ffecb1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800bfae1c0 (virt) @ffecb1c0 (dma) 0x070001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae1c4 (virt) @ffecb1c4 (dma) 0x10003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae1c8 (virt) @ffecb1c8 (dma) 0xffebe001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae1d0 (virt) @ffecb1d0 (dma) 0x100010 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae1d4 (virt) @ffecb1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1d8 (virt) @ffecb1d8 (dma) 0x32c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1dc (virt) @ffecb1dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1e0 (virt) @ffecb1e0 (dma) 0x2000c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1e8 (virt) @ffecb1e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1f0 (virt) @ffecb1f0 (dma) 0x38300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1f8 (virt) @ffecb1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Endpoint 0x83 ep reset callback called
usb 1-3.1: adding 1-3.1:2.0 (config #2, interface 0)
tegra-xusb 3610000.xhci: Waiting for status stage event
r8152 1-3.1:2.0: usb_probe_interface
r8152 1-3.1:2.0: usb_probe_interface - got id
cdc_ether 1-3.1:2.0: usb_probe_interface
cdc_ether 1-3.1:2.0: usb_probe_interface - got id
usb 1-3.1: adding 1-3.1:2.1 (config #2, interface 1)
usb 1-3.1: unregistering interface 1-3.1:2.0
usb 1-3.1: unregistering interface 1-3.1:2.1
usb 1-3.1: usb_disable_device nuking non-ep0 URBs
tegra-xusb 3610000.xhci: xhci_drop_endpoint called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: drop ep 0x83, slot id 2, new drop flags = 0x80, new add flags = 0x0
tegra-xusb 3610000.xhci: xhci_check_bandwidth called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: New Input Control Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000080 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000001 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful Endpoint Configure command
tegra-xusb 3610000.xhci: Output context after successful config ep cmd:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x10000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x1020103 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc2c1 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x8000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Cached old ring, 1 ring cached
tegra-xusb 3610000.xhci: add ep 0x81, slot id 2, new drop flags = 0x0, new add flags = 0x8
tegra-xusb 3610000.xhci: add ep 0x2, slot id 2, new drop flags = 0x0, new add flags = 0x18
tegra-xusb 3610000.xhci: add ep 0x83, slot id 2, new drop flags = 0x0, new add flags = 0x98
tegra-xusb 3610000.xhci: xhci_check_bandwidth called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: New Input Control Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000099 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0xffec1001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800adae140 (virt) @ffece140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae144 (virt) @ffece144 (dma) 0x2000016 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae148 (virt) @ffece148 (dma) 0xffec2001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae150 (virt) @ffece150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae154 (virt) @ffece154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae158 (virt) @ffece158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae15c (virt) @ffece15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae160 (virt) @ffece160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae168 (virt) @ffece168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae170 (virt) @ffece170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae178 (virt) @ffece178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800adae180 (virt) @ffece180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae184 (virt) @ffece184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae188 (virt) @ffece188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae190 (virt) @ffece190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae194 (virt) @ffece194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae198 (virt) @ffece198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae19c (virt) @ffece19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1a0 (virt) @ffece1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1a8 (virt) @ffece1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1b0 (virt) @ffece1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1b8 (virt) @ffece1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800adae1c0 (virt) @ffece1c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae1c4 (virt) @ffece1c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae1c8 (virt) @ffece1c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae1d0 (virt) @ffece1d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae1d4 (virt) @ffece1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae1d8 (virt) @ffece1d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae1dc (virt) @ffece1dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1e0 (virt) @ffece1e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1e8 (virt) @ffece1e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1f0 (virt) @ffece1f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1f8 (virt) @ffece1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800adae200 (virt) @ffece200 (dma) 0x070000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae204 (virt) @ffece204 (dma) 0x02003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae208 (virt) @ffece208 (dma) 0xffec4001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae210 (virt) @ffece210 (dma) 0x020002 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae214 (virt) @ffece214 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae218 (virt) @ffece218 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae21c (virt) @ffece21c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae220 (virt) @ffece220 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae228 (virt) @ffece228 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae230 (virt) @ffece230 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae238 (virt) @ffece238 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful Endpoint Configure command
tegra-xusb 3610000.xhci: Output context after successful config ep cmd:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x18000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x1020403 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc2c1 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x8000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0xffec1001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x18300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800bfae100 (virt) @ffecb100 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae104 (virt) @ffecb104 (dma) 0x2000016 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae108 (virt) @ffecb108 (dma) 0xffec2001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae110 (virt) @ffecb110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae114 (virt) @ffecb114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae118 (virt) @ffecb118 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae11c (virt) @ffecb11c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae120 (virt) @ffecb120 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae128 (virt) @ffecb128 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae130 (virt) @ffecb130 (dma) 0x20300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae138 (virt) @ffecb138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800bfae140 (virt) @ffecb140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae144 (virt) @ffecb144 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae148 (virt) @ffecb148 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae150 (virt) @ffecb150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae154 (virt) @ffecb154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae158 (virt) @ffecb158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae15c (virt) @ffecb15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae160 (virt) @ffecb160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae168 (virt) @ffecb168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae170 (virt) @ffecb170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae178 (virt) @ffecb178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800bfae180 (virt) @ffecb180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae184 (virt) @ffecb184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae188 (virt) @ffecb188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae190 (virt) @ffecb190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae194 (virt) @ffecb194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae198 (virt) @ffecb198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae19c (virt) @ffecb19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1a0 (virt) @ffecb1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1a8 (virt) @ffecb1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1b0 (virt) @ffecb1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1b8 (virt) @ffecb1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800bfae1c0 (virt) @ffecb1c0 (dma) 0x070001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae1c4 (virt) @ffecb1c4 (dma) 0x02003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae1c8 (virt) @ffecb1c8 (dma) 0xffec4001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae1d0 (virt) @ffecb1d0 (dma) 0x020002 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae1d4 (virt) @ffecb1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1d8 (virt) @ffecb1d8 (dma) 0x32c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1dc (virt) @ffecb1dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1e0 (virt) @ffecb1e0 (dma) 0x2000c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1e8 (virt) @ffecb1e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1f0 (virt) @ffecb1f0 (dma) 0x38300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1f8 (virt) @ffecb1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Endpoint 0x81 ep reset callback called
tegra-xusb 3610000.xhci: Endpoint 0x2 ep reset callback called
tegra-xusb 3610000.xhci: Endpoint 0x83 ep reset callback called
usb 1-3.1: adding 1-3.1:1.0 (config #1, interface 0)
r8152 1-3.1:1.0: usb_probe_interface
r8152 1-3.1:1.0: usb_probe_interface - got id
tegra-xusb 3610000.xhci: Endpoint 0x0 ep reset callback called
tegra-xusb 3610000.xhci: Resetting device with slot ID 2
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Completed reset device command.
tegra-xusb 3610000.xhci: Successful reset device command.
tegra-xusb 3610000.xhci: Cached old ring, 2 rings cached
tegra-xusb 3610000.xhci: Cached old ring, 3 rings cached
tegra-xusb 3610000.xhci: Cached old ring, 4 rings cached
tegra-xusb 3610000.xhci: Output context after successful reset device cmd:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x8000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x1020403 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc311 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000000080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0xffec1001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x18300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800bfae100 (virt) @ffecb100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae104 (virt) @ffecb104 (dma) 0x2000016 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae108 (virt) @ffecb108 (dma) 0xffec2001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae110 (virt) @ffecb110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae114 (virt) @ffecb114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae118 (virt) @ffecb118 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae11c (virt) @ffecb11c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae120 (virt) @ffecb120 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae128 (virt) @ffecb128 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae130 (virt) @ffecb130 (dma) 0x20300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae138 (virt) @ffecb138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800bfae140 (virt) @ffecb140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae144 (virt) @ffecb144 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae148 (virt) @ffecb148 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae150 (virt) @ffecb150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae154 (virt) @ffecb154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae158 (virt) @ffecb158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae15c (virt) @ffecb15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae160 (virt) @ffecb160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae168 (virt) @ffecb168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae170 (virt) @ffecb170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae178 (virt) @ffecb178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800bfae180 (virt) @ffecb180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae184 (virt) @ffecb184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae188 (virt) @ffecb188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae190 (virt) @ffecb190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae194 (virt) @ffecb194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae198 (virt) @ffecb198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae19c (virt) @ffecb19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1a0 (virt) @ffecb1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1a8 (virt) @ffecb1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1b0 (virt) @ffecb1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1b8 (virt) @ffecb1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800bfae1c0 (virt) @ffecb1c0 (dma) 0x070000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae1c4 (virt) @ffecb1c4 (dma) 0x02003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae1c8 (virt) @ffecb1c8 (dma) 0xffec4001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae1d0 (virt) @ffecb1d0 (dma) 0x020002 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae1d4 (virt) @ffecb1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1d8 (virt) @ffecb1d8 (dma) 0x32c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1dc (virt) @ffecb1dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1e0 (virt) @ffecb1e0 (dma) 0x2000c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1e8 (virt) @ffecb1e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1f0 (virt) @ffecb1f0 (dma) 0x38300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1f8 (virt) @ffecb1f8 (dma) 0x000000 - rsvd64[3]
usb 1-3.1: reset high-speed USB device number 5 using tegra-xusb
tegra-xusb 3610000.xhci: Slot ID 2 Input Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000003 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc311 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful setup address command
tegra-xusb 3610000.xhci: Op regs DCBAA ptr = 0x000000ffedf000
tegra-xusb 3610000.xhci: Slot ID 2 dcbaa entry @ffffff800a9bd010 = 0x000000ffecb000
tegra-xusb 3610000.xhci: Output Context DMA address = 0xffecb000
tegra-xusb 3610000.xhci: Slot ID 2 Input Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000003 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc311 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot ID 2 Output Context:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x8300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x10000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x020103 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc311 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0xffec1001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x18300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Internal device address = 2
tegra-xusb 3610000.xhci: Endpoint 0x0 ep reset callback called
usb 1-3.1: USB quirks for this device: 400
tegra-xusb 3610000.xhci: Waiting for status stage event
tegra-xusb 3610000.xhci: xhci_drop_endpoint called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: xhci_drop_endpoint called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: xhci_drop_endpoint called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: add ep 0x81, slot id 2, new drop flags = 0x0, new add flags = 0x8
tegra-xusb 3610000.xhci: add ep 0x2, slot id 2, new drop flags = 0x0, new add flags = 0x18
tegra-xusb 3610000.xhci: add ep 0x83, slot id 2, new drop flags = 0x0, new add flags = 0x98
tegra-xusb 3610000.xhci: xhci_check_bandwidth called for udev ffffffc1830af800
tegra-xusb 3610000.xhci: New Input Control Context:
tegra-xusb 3610000.xhci: @ffffff800adae000 (virt) @ffece000 (dma) 0x000000 - drop flags
tegra-xusb 3610000.xhci: @ffffff800adae004 (virt) @ffece004 (dma) 0x000099 - add flags
tegra-xusb 3610000.xhci: @ffffff800adae008 (virt) @ffece008 (dma) 0x000000 - rsvd2[0]
tegra-xusb 3610000.xhci: @ffffff800adae00c (virt) @ffece00c (dma) 0x000000 - rsvd2[1]
tegra-xusb 3610000.xhci: @ffffff800adae010 (virt) @ffece010 (dma) 0x000000 - rsvd2[2]
tegra-xusb 3610000.xhci: @ffffff800adae014 (virt) @ffece014 (dma) 0x000000 - rsvd2[3]
tegra-xusb 3610000.xhci: @ffffff800adae018 (virt) @ffece018 (dma) 0x000000 - rsvd2[4]
tegra-xusb 3610000.xhci: @ffffff800adae01c (virt) @ffece01c (dma) 0x000000 - rsvd2[5]
tegra-xusb 3610000.xhci: @ffffff800adae020 (virt) @ffece020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae028 (virt) @ffece028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae030 (virt) @ffece030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae038 (virt) @ffece038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800adae040 (virt) @ffece040 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800adae044 (virt) @ffece044 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800adae048 (virt) @ffece048 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800adae04c (virt) @ffece04c (dma) 0x000000 - dev_state
tegra-xusb 3610000.xhci: @ffffff800adae050 (virt) @ffece050 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae054 (virt) @ffece054 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae058 (virt) @ffece058 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae05c (virt) @ffece05c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800adae060 (virt) @ffece060 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae068 (virt) @ffece068 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae070 (virt) @ffece070 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae078 (virt) @ffece078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800adae080 (virt) @ffece080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae084 (virt) @ffece084 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae088 (virt) @ffece088 (dma) 0xffebc311 - deq
tegra-xusb 3610000.xhci: @ffffff800adae090 (virt) @ffece090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae094 (virt) @ffece094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae098 (virt) @ffece098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae09c (virt) @ffece09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0a0 (virt) @ffece0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0a8 (virt) @ffece0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0b0 (virt) @ffece0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0b8 (virt) @ffece0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800adae0c0 (virt) @ffece0c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae0c4 (virt) @ffece0c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae0c8 (virt) @ffece0c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae0d0 (virt) @ffece0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae0d4 (virt) @ffece0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae0d8 (virt) @ffece0d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae0dc (virt) @ffece0dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae0e0 (virt) @ffece0e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae0e8 (virt) @ffece0e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae0f0 (virt) @ffece0f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae0f8 (virt) @ffece0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800adae100 (virt) @ffece100 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae104 (virt) @ffece104 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae108 (virt) @ffece108 (dma) 0xffec6001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae110 (virt) @ffece110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae114 (virt) @ffece114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae118 (virt) @ffece118 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae11c (virt) @ffece11c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae120 (virt) @ffece120 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae128 (virt) @ffece128 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae130 (virt) @ffece130 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae138 (virt) @ffece138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800adae140 (virt) @ffece140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae144 (virt) @ffece144 (dma) 0x2000016 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae148 (virt) @ffece148 (dma) 0xffec9001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae150 (virt) @ffece150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae154 (virt) @ffece154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae158 (virt) @ffece158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae15c (virt) @ffece15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae160 (virt) @ffece160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae168 (virt) @ffece168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae170 (virt) @ffece170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae178 (virt) @ffece178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800adae180 (virt) @ffece180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae184 (virt) @ffece184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae188 (virt) @ffece188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae190 (virt) @ffece190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae194 (virt) @ffece194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae198 (virt) @ffece198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae19c (virt) @ffece19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1a0 (virt) @ffece1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1a8 (virt) @ffece1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1b0 (virt) @ffece1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1b8 (virt) @ffece1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800adae1c0 (virt) @ffece1c0 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae1c4 (virt) @ffece1c4 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae1c8 (virt) @ffece1c8 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800adae1d0 (virt) @ffece1d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae1d4 (virt) @ffece1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae1d8 (virt) @ffece1d8 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae1dc (virt) @ffece1dc (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae1e0 (virt) @ffece1e0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae1e8 (virt) @ffece1e8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae1f0 (virt) @ffece1f0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae1f8 (virt) @ffece1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800adae200 (virt) @ffece200 (dma) 0x070000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800adae204 (virt) @ffece204 (dma) 0x02003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800adae208 (virt) @ffece208 (dma) 0xffeca001 - deq
tegra-xusb 3610000.xhci: @ffffff800adae210 (virt) @ffece210 (dma) 0x020002 - tx_info
tegra-xusb 3610000.xhci: @ffffff800adae214 (virt) @ffece214 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800adae218 (virt) @ffece218 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800adae21c (virt) @ffece21c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800adae220 (virt) @ffece220 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800adae228 (virt) @ffece228 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800adae230 (virt) @ffece230 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800adae238 (virt) @ffece238 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: // Ding dong!
tegra-xusb 3610000.xhci: Successful Endpoint Configure command
tegra-xusb 3610000.xhci: Output context after successful config ep cmd:
tegra-xusb 3610000.xhci: Slot Context:
tegra-xusb 3610000.xhci: @ffffff800bfae000 (virt) @ffecb000 (dma) 0x38300001 - dev_info
tegra-xusb 3610000.xhci: @ffffff800bfae004 (virt) @ffecb004 (dma) 0x070000 - dev_info2
tegra-xusb 3610000.xhci: @ffffff800bfae008 (virt) @ffecb008 (dma) 0x000000 - tt_info
tegra-xusb 3610000.xhci: @ffffff800bfae00c (virt) @ffecb00c (dma) 0x18000002 - dev_state
tegra-xusb 3610000.xhci: @ffffff800bfae010 (virt) @ffecb010 (dma) 0x1020403 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae014 (virt) @ffecb014 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae018 (virt) @ffecb018 (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae01c (virt) @ffecb01c (dma) 0x000000 - rsvd[3]
tegra-xusb 3610000.xhci: @ffffff800bfae020 (virt) @ffecb020 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae028 (virt) @ffecb028 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae030 (virt) @ffecb030 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae038 (virt) @ffecb038 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 00 Context (ep_index 00):
tegra-xusb 3610000.xhci: @ffffff800bfae040 (virt) @ffecb040 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae044 (virt) @ffecb044 (dma) 0x400026 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae048 (virt) @ffecb048 (dma) 0xffebc461 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae050 (virt) @ffecb050 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae054 (virt) @ffecb054 (dma) 0x8000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae058 (virt) @ffecb058 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae05c (virt) @ffecb05c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae060 (virt) @ffecb060 (dma) 0x00c080 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae068 (virt) @ffecb068 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae070 (virt) @ffecb070 (dma) 0x8300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae078 (virt) @ffecb078 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 01 Context (ep_index 01):
tegra-xusb 3610000.xhci: @ffffff800bfae080 (virt) @ffecb080 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae084 (virt) @ffecb084 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae088 (virt) @ffecb088 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae090 (virt) @ffecb090 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae094 (virt) @ffecb094 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae098 (virt) @ffecb098 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae09c (virt) @ffecb09c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0a0 (virt) @ffecb0a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0a8 (virt) @ffecb0a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0b0 (virt) @ffecb0b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0b8 (virt) @ffecb0b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 01 Context (ep_index 02):
tegra-xusb 3610000.xhci: @ffffff800bfae0c0 (virt) @ffecb0c0 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae0c4 (virt) @ffecb0c4 (dma) 0x2000036 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae0c8 (virt) @ffecb0c8 (dma) 0xffec6001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae0d0 (virt) @ffecb0d0 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae0d4 (virt) @ffecb0d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0d8 (virt) @ffecb0d8 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0dc (virt) @ffecb0dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0e0 (virt) @ffecb0e0 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae0e8 (virt) @ffecb0e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae0f0 (virt) @ffecb0f0 (dma) 0x18300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae0f8 (virt) @ffecb0f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 02 Context (ep_index 03):
tegra-xusb 3610000.xhci: @ffffff800bfae100 (virt) @ffecb100 (dma) 0x000001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae104 (virt) @ffecb104 (dma) 0x2000016 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae108 (virt) @ffecb108 (dma) 0xffec9001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae110 (virt) @ffecb110 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae114 (virt) @ffecb114 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae118 (virt) @ffecb118 (dma) 0x12c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae11c (virt) @ffecb11c (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae120 (virt) @ffecb120 (dma) 0x00c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae128 (virt) @ffecb128 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae130 (virt) @ffecb130 (dma) 0x20300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae138 (virt) @ffecb138 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 02 Context (ep_index 04):
tegra-xusb 3610000.xhci: @ffffff800bfae140 (virt) @ffecb140 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae144 (virt) @ffecb144 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae148 (virt) @ffecb148 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae150 (virt) @ffecb150 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae154 (virt) @ffecb154 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae158 (virt) @ffecb158 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae15c (virt) @ffecb15c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae160 (virt) @ffecb160 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae168 (virt) @ffecb168 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae170 (virt) @ffecb170 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae178 (virt) @ffecb178 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: OUT Endpoint 03 Context (ep_index 05):
tegra-xusb 3610000.xhci: @ffffff800bfae180 (virt) @ffecb180 (dma) 0x000000 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae184 (virt) @ffecb184 (dma) 0x000000 - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae188 (virt) @ffecb188 (dma) 0x000000 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae190 (virt) @ffecb190 (dma) 0x000000 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae194 (virt) @ffecb194 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae198 (virt) @ffecb198 (dma) 0x000000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae19c (virt) @ffecb19c (dma) 0x000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1a0 (virt) @ffecb1a0 (dma) 0x000000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1a8 (virt) @ffecb1a8 (dma) 0x000000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1b0 (virt) @ffecb1b0 (dma) 0x000000 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1b8 (virt) @ffecb1b8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: IN Endpoint 03 Context (ep_index 06):
tegra-xusb 3610000.xhci: @ffffff800bfae1c0 (virt) @ffecb1c0 (dma) 0x070001 - ep_info
tegra-xusb 3610000.xhci: @ffffff800bfae1c4 (virt) @ffecb1c4 (dma) 0x02003e - ep_info2
tegra-xusb 3610000.xhci: @ffffff800bfae1c8 (virt) @ffecb1c8 (dma) 0xffeca001 - deq
tegra-xusb 3610000.xhci: @ffffff800bfae1d0 (virt) @ffecb1d0 (dma) 0x020002 - tx_info
tegra-xusb 3610000.xhci: @ffffff800bfae1d4 (virt) @ffecb1d4 (dma) 0x000000 - rsvd[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1d8 (virt) @ffecb1d8 (dma) 0x32c0000 - rsvd[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1dc (virt) @ffecb1dc (dma) 0x8000000 - rsvd[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1e0 (virt) @ffecb1e0 (dma) 0x2000c000 - rsvd64[0]
tegra-xusb 3610000.xhci: @ffffff800bfae1e8 (virt) @ffecb1e8 (dma) 0x200000200080000 - rsvd64[1]
tegra-xusb 3610000.xhci: @ffffff800bfae1f0 (virt) @ffecb1f0 (dma) 0x38300001 - rsvd64[2]
tegra-xusb 3610000.xhci: @ffffff800bfae1f8 (virt) @ffecb1f8 (dma) 0x000000 - rsvd64[3]
tegra-xusb 3610000.xhci: Endpoint 0x81 ep reset callback called
tegra-xusb 3610000.xhci: Endpoint 0x2 ep reset callback called
tegra-xusb 3610000.xhci: Endpoint 0x83 ep reset callback called
r8152 1-3.1:1.0 eth2: v2.09.00 (2017/08/21)
r8152 1-3.1:1.0 eth2: This product is covered by one or more of the following patents:
		US6,570,884, US6,115,776, and US6,327,625.