diff -Naur r28.2.1-orig/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-ar0144-a00.dtsi r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-ar0144-a00.dtsi --- r28.2.1-orig/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-ar0144-a00.dtsi Thu Jan 1 01:00:00 1970 +++ r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-ar0144-a00.dtsi Thu Oct 18 11:33:04 2018 @@ -0,0 +1,688 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/ { + host1x { + vi@15700000 { + num-channels = <3>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_vi_in0: endpoint { + csi-port = <0>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_out0>; + }; + }; + port@1 { + reg = <1>; + liar0144_vi_in1: endpoint { + csi-port = <2>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_out1>; + }; + }; + port@2 { + reg = <2>; + liar0144_vi_in2: endpoint { + csi-port = <4>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_out2>; + }; + }; + }; + }; + + nvcsi@150c0000 { + num-channels = <3>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_csi_in0: endpoint@0 { + csi-port = <0>; + bus-width = <2>; + remote-endpoint = <&liar0144_ar0144_out0>; + }; + }; + port@1 { + reg = <1>; + liar0144_csi_out0: endpoint@1 { + remote-endpoint = <&liar0144_vi_in0>; + }; + }; + }; + }; + channel@1 { + reg = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_csi_in1: endpoint@0 { + csi-port = <2>; + bus-width = <2>; + remote-endpoint = <&liar0144_ar0144_out1>; + }; + }; + port@1 { + reg = <1>; + liar0144_csi_out1: endpoint@1 { + remote-endpoint = <&liar0144_vi_in1>; + }; + }; + }; + }; + channel@2 { + reg = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_csi_in2: endpoint@0 { + csi-port = <4>; + bus-width = <2>; + remote-endpoint = <&liar0144_ar0144_out2>; + }; + }; + port@1 { + reg = <1>; + liar0144_csi_out2: endpoint@1 { + remote-endpoint = <&liar0144_vi_in2>; + }; + }; + }; + }; + }; + }; + + i2c@3180000 { + tca9546@70 { + i2c@0 { + ar0144_a@10 { + compatible = "nvidia,ar0144"; + /* I2C device address */ + reg = <0x10>; + + /* V4L2 device node location */ + /*devnode = "video0";*/ + + /* Physical dimensions of sensor */ + physical_w = "1.948"; + physical_h = "1.109"; + + + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + avdd-reg = "vana"; + iovdd-reg = "vif"; + dvdd-reg = "vdig"; + sensor_model ="ar0144"; + + /* Defines number of frames to be dropped by driver internally after applying */ + /* sensor crop settings. Some sensors send corrupt frames after applying */ + /* crop co-ordinates */ + post_crop_frame_drop = "0"; + + /* if true, delay gain setting by one frame to be in sync with exposure */ + delayed_gain = "true"; + + /** + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * mclk_khz = ""; + * Standard MIPI driving clock, typically 24MHz + * + * num_lanes = ""; + * Number of lane channels sensor is programmed to output + * + * tegra_sinterface = ""; + * The base tegra serial interface lanes are connected to + * + * discontinuous_clk = ""; + * The sensor is programmed to use a discontinuous clock on MIPI lanes + * + * dpcm_enable = "true"; + * The sensor is programmed to use a DPCM modes + * + * cil_settletime = ""; + * MIPI lane settle time value. + * A "0" value attempts to autocalibrate based on mclk_multiplier + * + * + * + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * This is used to calibrate features in our camera stack. + * + * mclk_multiplier = ""; + * Multiplier to MCLK to help time hardware capture sequence + * TODO: Assign to PLL_Multiplier as well until fixed in core + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * + * + * + * inherent_gain = ""; + * Gain obtained inherently from mode (ie. pixel binning) + * + * min_gain_val = ""; (floor to 6 decimal places) + * max_gain_val = ""; (floor to 6 decimal places) + * Gain limits for mode + * + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (us) + * + * + * min_hdr_ratio = ""; + * max_hdr_ratio = ""; + * HDR Ratio limits for mode + * + * min_framerate = ""; + * max_framerate = ""; + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 {/*mode AR0144_MODE_1920X1080_CROP_30FPS*/ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_a"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + + dynamic_pixel_bit_depth = "12"; + csi_pixel_bit_depth = "12"; + mode_type = "bayer"; + pixel_phase = "rggb"; + pixel_t = "bayer_rggb"; + + + active_w = "1280"; + active_h = "720"; + readout_orientation = "0"; + line_length = "1488"; + inherent_gain = "1"; + mclk_multiplier = "25"; + pix_clk_hz = "74250000"; + + min_gain_val = "1"; + max_gain_val = "31"; + min_hdr_ratio = "1"; + max_hdr_ratio = "64"; + min_framerate = "6"; + max_framerate = "60"; + min_exp_time = "200"; + max_exp_time = "166332"; + embedded_metadata_height = "4"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_ar0144_out0: endpoint { + csi-port = <0>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_in0>; + }; + }; + }; + }; + }; + i2c@1 { + ar0144_b@10 { + compatible = "nvidia,ar0144"; + /* I2C device address */ + reg = <0x10>; + + /* V4L2 device node location */ + /*devnode = "video1";*/ + + /* Physical dimensions of sensor */ + physical_w = "1.948"; + physical_h = "1.109"; + + + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + avdd-reg = "vana"; + iovdd-reg = "vif"; + dvdd-reg = "vdig"; + sensor_model ="ar0144"; + + /* Defines number of frames to be dropped by driver internally after applying */ + /* sensor crop settings. Some sensors send corrupt frames after applying */ + /* crop co-ordinates */ + post_crop_frame_drop = "0"; + + /* if true, delay gain setting by one frame to be in sync with exposure */ + delayed_gain = "true"; + + /** + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * mclk_khz = ""; + * Standard MIPI driving clock, typically 24MHz + * + * num_lanes = ""; + * Number of lane channels sensor is programmed to output + * + * tegra_sinterface = ""; + * The base tegra serial interface lanes are connected to + * + * discontinuous_clk = ""; + * The sensor is programmed to use a discontinuous clock on MIPI lanes + * + * dpcm_enable = "true"; + * The sensor is programmed to use a DPCM modes + * + * cil_settletime = ""; + * MIPI lane settle time value. + * A "0" value attempts to autocalibrate based on mclk_multiplier + * + * + * + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * This is used to calibrate features in our camera stack. + * + * mclk_multiplier = ""; + * Multiplier to MCLK to help time hardware capture sequence + * TODO: Assign to PLL_Multiplier as well until fixed in core + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * + * + * + * inherent_gain = ""; + * Gain obtained inherently from mode (ie. pixel binning) + * + * min_gain_val = ""; (floor to 6 decimal places) + * max_gain_val = ""; (floor to 6 decimal places) + * Gain limits for mode + * + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (us) + * + * + * min_hdr_ratio = ""; + * max_hdr_ratio = ""; + * HDR Ratio limits for mode + * + * min_framerate = ""; + * max_framerate = ""; + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 {/*mode AR0144_MODE_1920X1080_CROP_30FPS*/ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_c"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + + dynamic_pixel_bit_depth = "12"; + csi_pixel_bit_depth = "12"; + mode_type = "bayer"; + pixel_phase = "rggb"; + pixel_t = "bayer_rggb"; + + active_w = "1280"; + active_h = "720"; + readout_orientation = "0"; + line_length = "1488"; + inherent_gain = "1"; + mclk_multiplier = "25"; + pix_clk_hz = "74250000"; + + min_gain_val = "1"; /* dB */ + max_gain_val = "31"; /* dB */ + min_hdr_ratio = "1"; + max_hdr_ratio = "64"; + min_framerate = "6"; + max_framerate = "60"; + min_exp_time = "200"; + max_exp_time = "166332"; + embedded_metadata_height = "4"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_ar0144_out1: endpoint { + csi-port = <2>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_in1>; + }; + }; + }; + }; + }; + i2c@2 { + ar0144_c@10 { + compatible = "nvidia,ar0144"; + /* I2C device address */ + reg = <0x10>; + + /* V4L2 device node location */ + /*devnode = "video2";*/ + + /* Physical dimensions of sensor */ + physical_w = "1.948"; + physical_h = "1.109"; + + + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + avdd-reg = "vana"; + iovdd-reg = "vif"; + dvdd-reg = "vdig"; + sensor_model ="ar0144"; + + /* Defines number of frames to be dropped by driver internally after applying */ + /* sensor crop settings. Some sensors send corrupt frames after applying */ + /* crop co-ordinates */ + post_crop_frame_drop = "0"; + + /* if true, delay gain setting by one frame to be in sync with exposure */ + delayed_gain = "true"; + + /** + * A modeX node is required to support v4l2 driver + * implementation with NVIDIA camera software stack + * + * mclk_khz = ""; + * Standard MIPI driving clock, typically 24MHz + * + * num_lanes = ""; + * Number of lane channels sensor is programmed to output + * + * tegra_sinterface = ""; + * The base tegra serial interface lanes are connected to + * + * discontinuous_clk = ""; + * The sensor is programmed to use a discontinuous clock on MIPI lanes + * + * dpcm_enable = "true"; + * The sensor is programmed to use a DPCM modes + * + * cil_settletime = ""; + * MIPI lane settle time value. + * A "0" value attempts to autocalibrate based on mclk_multiplier + * + * + * + * + * active_w = ""; + * Pixel active region width + * + * active_h = ""; + * Pixel active region height + * + * pixel_t = ""; + * The sensor readout pixel pattern + * + * readout_orientation = "0"; + * Based on camera module orientation. + * Only change readout_orientation if you specifically + * Program a different readout order for this mode + * + * line_length = ""; + * Pixel line length (width) for sensor mode. + * This is used to calibrate features in our camera stack. + * + * mclk_multiplier = ""; + * Multiplier to MCLK to help time hardware capture sequence + * TODO: Assign to PLL_Multiplier as well until fixed in core + * + * pix_clk_hz = ""; + * Sensor pixel clock used for calculations like exposure and framerate + * + * + * + * + * inherent_gain = ""; + * Gain obtained inherently from mode (ie. pixel binning) + * + * min_gain_val = ""; (floor to 6 decimal places) + * max_gain_val = ""; (floor to 6 decimal places) + * Gain limits for mode + * + * min_exp_time = ""; (ceil to integer) + * max_exp_time = ""; (ceil to integer) + * Exposure Time limits for mode (us) + * + * + * min_hdr_ratio = ""; + * max_hdr_ratio = ""; + * HDR Ratio limits for mode + * + * min_framerate = ""; + * max_framerate = ""; + * Framerate limits for mode (fps) + * + * embedded_metadata_height = ""; + * Sensor embedded metadata height in units of rows. + * If sensor does not support embedded metadata value should be 0. + */ + mode0 {/*mode AR0144_MODE_1920X1080_CROP_30FPS*/ + mclk_khz = "24000"; + num_lanes = "2"; + tegra_sinterface = "serial_e"; + discontinuous_clk = "yes"; + dpcm_enable = "false"; + cil_settletime = "0"; + + dynamic_pixel_bit_depth = "12"; + csi_pixel_bit_depth = "12"; + mode_type = "bayer"; + pixel_phase = "rggb"; + pixel_t = "bayer_rggb"; + + active_w = "1280"; + active_h = "720"; + readout_orientation = "0"; + line_length = "1488"; + inherent_gain = "1"; + mclk_multiplier = "25"; + pix_clk_hz = "74250000"; + + min_gain_val = "1"; /* dB */ + max_gain_val = "31"; /* dB */ + min_hdr_ratio = "1"; + max_hdr_ratio = "64"; + min_framerate = "6"; + max_framerate = "60"; + min_exp_time = "200"; + max_exp_time = "166332"; + embedded_metadata_height = "4"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + liar0144_ar0144_out2: endpoint { + csi-port = <4>; + bus-width = <2>; + remote-endpoint = <&liar0144_csi_in2>; + }; + }; + }; + }; + }; + }; + }; +}; + + + +/ { + + tegra-camera-platform { + compatible = "nvidia, tegra-camera-platform"; + /** + * Physical settings to calculate max ISO BW + * + * num_csi_lanes = <>; + * Total number of CSI lanes when all cameras are active + * + * max_lane_speed = <>; + * Max lane speed in Kbit/s + * + * min_bits_per_pixel = <>; + * Min bits per pixel + * + * vi_peak_byte_per_pixel = <>; + * Max byte per pixel for the VI ISO case + * + * vi_bw_margin_pct = <>; + * Vi bandwidth margin in percentage + * + * max_pixel_rate = <>; + * Max pixel rate in Kpixel/s for the ISP ISO case + * + * isp_peak_byte_per_pixel = <>; + * Max byte per pixel for the ISP ISO case + * + * isp_bw_margin_pct = <>; + * Isp bandwidth margin in percentage + */ + num_csi_lanes = <6>; + max_lane_speed = <1500000>; + min_bits_per_pixel = <10>; + vi_peak_byte_per_pixel = <2>; + vi_bw_margin_pct = <25>; + isp_peak_byte_per_pixel = <5>; + isp_bw_margin_pct = <25>; + + /** + * The general guideline for naming badge_info contains 3 parts, and is as follows, + * The first part is the camera_board_id for the module; if the module is in a FFD + * platform, then use the platform name for this part. + * The second part contains the position of the module, ex. "rear" or "front". + * The third part contains the last 6 characters of a part number which is found + * in the module's specsheet from the vender. + */ + modules { + module2 { + badge = "ar0144_bottomleft_liar0144"; + position = "bottomleft"; + orientation = "1"; + status = "okay"; + drivernode0 { + /* Declare PCL support driver (classically known as guid) */ + pcl_id = "v4l2_sensor"; + /* Driver v4l2 device name */ + devname = "ar0144 30-0010"; + /* Declare the device-tree hierarchy to driver instance */ + proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/ar0144_a@10"; + status = "okay"; + }; + }; + module1 { + badge = "ar0144_centerleft_liar0144"; + position = "centerleft"; + orientation = "1"; + status = "okay"; + drivernode0 { + /* Declare PCL support driver (classically known as guid) */ + pcl_id = "v4l2_sensor"; + /* Driver v4l2 device name */ + devname = "ar0144 31-0010"; + /* Declare the device-tree hierarchy to driver instance */ + proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@1/ar0144_b@10"; + status = "okay"; + }; + }; + module0 { + badge = "ar0144_centerright_liar0144"; + position = "centerright"; + orientation = "1"; + status = "okay"; + drivernode0 { + /* Declare PCL support driver (classically known as guid) */ + pcl_id = "v4l2_sensor"; + /* Driver v4l2 device name */ + devname = "ar0144 32-0010"; + /* Declare the device-tree hierarchy to driver instance */ + proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@2/ar0144_c@10"; + status = "okay"; + }; + }; + }; + }; +}; diff -Naur r28.2.1-orig/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-ar0144-a00.dtsi r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-ar0144-a00.dtsi --- r28.2.1-orig/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-ar0144-a00.dtsi Thu Jan 1 01:00:00 1970 +++ r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-ar0144-a00.dtsi Thu Oct 18 11:33:04 2018 @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include "dt-bindings/clock/tegra186-clock.h" + +#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5) +#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0) +#define CAM1_RST_L TEGRA_MAIN_GPIO(R, 1) +#define CAM1_PWDN TEGRA_MAIN_GPIO(L, 6) +#define CAMERA_I2C_MUX_BUS(x) (0x1E + x) + +/* camera control gpio definitions */ + +/ { + i2c@3180000 { + tca9546@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + skip_mux_detect = "yes"; + /*vif-supply = <&en_vdd_cam>;*/ + vcc-pullup-supply = <&en_vdd_cam>; + vcc-supply = <&en_vdd_cam>; + vcc_lp = "vcc"; + force_bus_start = ; + + i2c@0 { + reg = <0>; + i2c-mux,deselect-on-exit; + #address-cells = <1>; + #size-cells = <0>; + pca9570_a@24 { + compatible = "nvidia,pca9570"; + reg = <0x24>; + channel = "a"; + drive_ic = "DRV8838"; + }; + ar0144_a@10 { + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>, + <&tegra_car TEGRA186_CLK_PLLP_OUT0>; + clock-names = "extperiph1", "pllp_grtba"; + clock-frequency = <27000000>; + mclk = "extperiph1"; + reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>; + vana-supply = <&en_vdd_cam_hv_2v8>; + vif-supply = <&en_vdd_cam>; + vdig-supply = <&en_vdd_cam_1v2>; + + }; + }; + i2c@1 { + reg = <1>; + i2c-mux,deselect-on-exit; + #address-cells = <1>; + #size-cells = <0>; + pca9570_b@24 { + compatible = "nvidia,pca9570"; + reg = <0x24>; + channel = "b"; + drive_ic = "DRV8838"; + }; + ar0144_b@10 { + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH2>, + <&tegra_car TEGRA186_CLK_PLLP_OUT0>; + clock-names = "extperiph1", "pllp_grtba"; + clock-frequency = <27000000>; + mclk = "extperiph1"; + reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>; + vana-supply = <&en_vdd_cam_hv_2v8>; + vif-supply = <&en_vdd_cam>; + vdig-supply = <&en_vdd_cam_1v2>; + + }; + }; + i2c@2 { + reg = <2>; + i2c-mux,deselect-on-exit; + #address-cells = <1>; + #size-cells = <0>; + pca9570_c@24 { + compatible = "nvidia,pca9570"; + reg = <0x24>; + channel = "c"; + drive_ic = "DRV8838"; + }; + ar0144_c@10 { + /* Define any required hw resources needed by driver */ + /* ie. clocks, io pins, power sources */ + clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH3>, + <&tegra_car TEGRA186_CLK_PLLP_OUT0>; + clock-names = "extperiph1", "pllp_grtba"; + clock-frequency = <27000000>; + mclk = "extperiph1"; + /* + reset-gpios = <&gpio_i2c_0_77 9 1>; + */ + reset-gpios = <&gpio_i2c_0_77 7 GPIO_ACTIVE_HIGH>; + vana-supply = <&en_vdd_cam_hv_2v8>; + vif-supply = <&en_vdd_cam>; + vdig-supply = <&en_vdd_cam_1v2>; + }; + }; + }; + }; +}; diff -Naur r28.2.1-orig/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts --- r28.2.1-orig/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts Wed May 16 02:53:25 2018 +++ r28.2.1-3ar0144rggb-clean/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts Thu Oct 18 11:33:05 2018 @@ -15,7 +15,8 @@ #include #include -#include +//#include +#include "t18x-common-platforms/tegra186-quill-camera-ar0144-a00.dtsi" #include /* comms dtsi file should be included after gpio dtsi file */ @@ -24,7 +25,7 @@ #include #include #include -#include +//#include #include